DeNovo: Rethinking the memory hierarchy for disciplined parallelism

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2011, Pages 155-166

  Choi, Byn ^a   Komuravelli, Rakesh ^a   Sung, Hyojin ^a   Smolinski, Robert ^a   Honarmand, Nima ^a   Adve, Sarita V ^a   Adve, Vikram S ^a   Carter, Nicholas P ^b   Chou, Ching Tsun ^b  

^a University of Illinois at Urbana Champaign   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDITIONAL PROTOCOL; ADDRESS SPACE; CACHE ARCHITECTURE; CACHE COHERENCE; CACHE HIT RATES; COHERENCE PROTOCOL; DATA RACES; DESIGN COMPLEXITY; FLEXIBLE COMMUNICATION; HARDWARE ARCHITECTURE; HARDWARE DESIGNERS; MANY-CORE; MEMORY HIERARCHY; NETWORK TRAFFIC; NON-DETERMINISM; PARALLEL PROGRAMMING MODEL; SHARED MEMORIES; SHARED-MEMORY PROGRAMMING MODEL; SOFTWARE EVOLUTION; SOFTWARE MODEL; TRANSIENT STATE;

COMMUNICATION; MESSAGE PASSING; MODEL CHECKING; NETWORK ARCHITECTURE; PARALLEL ARCHITECTURES;

PARALLEL PROGRAMMING;

EID: 84856527825     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2011.21     Document Type: Conference Paper

References (72)

1. OpenSPARCTM T2 system-on-chip (soc) microarchitecture specification, May 2008.
2. H. Abdel-Shafi et al. An Evaluation of Fine-Grain Producer-Initiated Communication in Cache-Coherent Multiprocessors. In HPCA, 1997.
3. D. Abts et al. So Many States, So Little Time: Verifying Memory Coherence in the Cray X1. In IPDPS, 2003.
4. S. V. Adve and H.-J. Boehm. Memory Models: A Case for Rethinking Parallel Languages and Hardware. CACM, Aug. 2010.
5. S. V. Adve et al. A Comparison of Entry Consistency and Lazy Release Consistency. In HPCA, pages 26-37, February 1996.
6. S. V. Adve and M. D. Hill. Weak Ordering - A New Definition. In Proc. 17th Intl. Symp. on Computer Architecture, pages 2-14, May 1990.
7. V. S. Adve and L. Ceze. Workshop on Deterministic Multiprocessing and Parallel Programming, U-Washington, 2009.
8. N. Agarwal et al. Garnet: A detailed interconnection network model inside a full-system simulation framework. Technical Report CE-P08- 001, Princeton University, 2008.
9. M. D. Allen, S. Sridharan, and G. S. Sohi. Serialization Sets: A Dynamic Dependence-based Parallel Execution Model. In PPoPP, pages 85-96, 2009.
10. Z. Anderson et al. SharC: Checking Data Sharing Strategies for Multithreaded C. In PLDI, pages 149-158, 2008.
11. R. H. Arpaci et al. Empirical Evaluation of the CRAY-T3D: A Compiler Perspective. In ISCA, pages 320-331, June 1995.
12. A. Basu et al. Scavenger: A New Last Level Cache Architecture with Global Block Priority. In MICRO, 2007.
13. A. Baumann et al. The Multikernel: A New OS Architecture for Scalable Multicore Systems. In SOSP, 2009.
14. E. D. Berger et al. Grace: Safe Multithreaded Programming for C/C++. In OOPSLA, pages 81-96, 2009.
15. B. N. Bershad and M. J. Zekauskas. Midway: Shared memory parallel programming with entry consistency for distributed memory multiprocessors. Technical Report TR CMU-CS-91-170, CMU, 1991.
16. C. Bienia. Benchmarking Modern Multiprocessors. PhD thesis, Princeton University, Jan. 2011.
17. C. Bienia et al. Fidelity and scaling of the parsec benchmark inputs. In Workload Characterization (IISWC), 2010 IEEE International Symposium on, 2010.
18. R. D. Blumofe et al. Cilk: An Efficient Multithreaded Runtime System. In PPoPP, pages 207-216, 1995.
19. M. A. Blumrich et al. Virtual memory mapped network interface for the shrimp multicomputer. In ISCA, pages 142-153, 1994.
20. R. Bocchino et al. Safe Nondeterminism in a Deterministic-by-Default Parallel Language. In POPL, 2011. To appear.
21. R. L. Bocchino, Jr. et al. A Type and Effect System for Deterministic Parallel Java. In OOPSLA, pages 97-116, 2009.
22. Z. Budimlic et al. Multi-core Implementations of the Concurrent Collections Programming Model. In IWCPC, 2009.
23. J. Cantin et al. Improving Multiprocessor Performance with Coarse- Grain Coherence Tracking. In ISCA, pages 246-257, June 2005. (Pubitemid 41543445)
24. M. Castro et al. Efficient and flexible object sharing. Technical report, IST - INESC, Portugal, July 1995.
25. K. Chakraborty et al. Computation Spreading: Employing hardware migration to specialize CMP cores on-the-fly. In Proceedings of the 12th international conference on Architectural support for programming languages and operating systems, ASPLOS-XII, pages 283-292, New York, NY, USA, 2006. ACM.
26. R. Chandra et al. Performance Evaluation of Hybrid Hardware and Software Distributed Shared Memory Protocols. In ICS, 1994.
27. B. Choi et al. Parallel SAH k-D Tree Construction. In High Performance Graphics (HPG), 2010.
28. S. Curial et al. Mpads: memory-pooling-assisted data splitting. In ISMM, pages 101-110, 2008.
29. D. L. Dill et al. Protocol Verification as a Hardware Design Aid. In ICCD '92, pages 522-525, Washington, DC, USA, 1992. IEEE Computer Society.
30. M. Dubois et al. Delayed Consistency and its Effects on the Miss Rate of Parallel Programs. In SC, pages 197-206, 1991.
31. C. Fensch and M. Cintra. An OS-based alternative to full hardware coherence on tiled CMPs. In HPCA, 2008.
32. K. Gharachorloo et al. Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors. In ISCA, pages 15-26, May 1990.
33. A. Ghuloum et al. Ct: A Flexible Parallel Programming Model for Tera-Scale Architectures. Intel White Paper, 2007.
34. S. Gjessing et al. Formal specification and verification of sci cache coherence: The top layers. October 1989.
35. N. Gustafsson. Axum: Language Overview. Microsoft Language Specification, 2009.
36. D. Hackenberg et al. Comparing Cache Architectures and Coherency Protocols on x86-64 Multicore SMP Systems. In MICRO, pages 413- 422. IEEE, 2009.
37. N. Hardavellas et al. Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches. In ISCA, pages 184-195, 2009.
38. K. Hayashi et al. AP1000+: Architectural Support of PUT/GET Interface for Parallelizing Compiler. In ASPLOS, pages 196-207, 1994.
39. J. Heinlein et al. Coherent Block Data Transfer in the FLASH Multiprocessor. In ISPP, pages 18-27, 1997.
40. J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 4th edition, 2007.
41. J. Howard et al. A 48-core IA-32 Message-Passing Processor with DVFS in 45nm CMOS. In ISSCC, pages 108-109, 2010.
42. G. C. Hunt and J. R. Larus. Singularity: Rethinking the Software Stack. In ACM SIGOPS Operating Systems Review, 2007.
43. Intel. The SCC Platform Overview. http://techresearch.intel.com/spaw2/ uploads/files/SCC-Platform Overview.pdf.
44. T. E. Jeremiassen and S. J. Eggers. Reducing false sharing on shared memory multiprocessors through compile time data transformations. In PPOPP, pages 179-188, 1995.
45. S. Kaxiras and G. Keramidas. SARC Coherence: Scaling Directory Cache Coherence in Performance and Power. IEEE Micro, 30(5):54-65, Sept.-Oct. 2010.
46. P. Keleher, A. L. Cox, and W. Zwaenepoel. Lazy Release Consistency for Software Distributed Shared Memory. In ISCA, pages 13-21, 1992. (Pubitemid 23579916)
47. J. H. Kelm et al. Rigel: An Architecture and Scalable Programming Interface for a 1000-core Accelerator. In ISCA, 2009.
48. D. A. Koufaty et al. Data Forwarding in Scalable Shared-Memory Multiprocessors. In SC, pages 255-264, 1995.
49. M. Kulkarni et al. Optimistic Parallelism Requires Abstractions. In PLDI, pages 211-222, 2007. (Pubitemid 47630689)
50. A. Kumar et al. Efficient and scalable cache coherence schemes for shared memory hypercube multiprocessors. In SC, New York, NY, USA, 1994. ACM.
51. A. R. Lebeck and D. A. Wood. Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors. In ISCA, pages 48-59, Jun 1995.
52. E. A. Lee. The Problem with Threads. IEEE Computer, 39(5):33-42, May 2006. (Pubitemid 43786509)
53. B. Lucia et al. Conflict Exceptions: Simplifying Concurrent Language Semantics with Precise Hardware Exceptions for Data-Races. In ISCA, 2010.
54. M. M. Martin et al. Token coherence: Decoupling performance and correctness. In ISCA, 2003.
55. M. M. Martin et al. Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors. In ISCA, 2003.
56. M. M. K. Martin et al. Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset. SIGARCH Computer Architecture News, 33(4):92-99, 2005.
57. M. R. Marty et al. Improving Multiple-CMP Systems Using Token Coherence. In HPCA, pages 328-339, 2005. (Pubitemid 41731512)
58. S. L. Min and J.-L. Baer. Design and analysis of a scalable cache coherence scheme based on clocks and timestamps. IEEE Trans. on Parallel and Distributed Systems, 3(2):25-44, January 1992.
59. A. Moshovos. RegionScout: Exploiting Coarse Grain Sharing in Snoop- Based Coherence. In ISCA, 2005.
60. A. Nanda and L. Bhuyan. A formal specification and verification technique for cache coherence protocols. In ICPP, pages I22-I26, 1992.
61. M. Olszewski et al. Kendo: Efficient Deterministic Multithreading in Software. In ASPLOS, pages 97-108, 2009.
62. S. H. Pugsley et al. SWEL: Hardware Cache Coherence Protocols to Map Shared Data onto Shared Caches. In PACT, 2010.
63. A. Raghavan et al. Token Tenure: PATCHing Token Counting using Directory-Based Cache Coherence. In MICRO, 2008.
64. S. Somogyi et al. Spatial Memory Streaming. In ISCA, pages 252-263, 2006. (Pubitemid 46016620)
65. D. J. Sorin et al. Specifying and verifying a broadcast and a multicast snooping cache coherence protocol. IEEE Trans. Parallel Distrib. Syst., 13(6):556-578, 2002. (Pubitemid 34835456)
66. K. Strauss et al. Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors. In ISCA, pages 327-338, 2006. (Pubitemid 46016626)
67. D. Vantrease et al. Atomic Coherence: Leveraging Nanophotonics to Build Race-Free Cache Coherence Protocols. In HPCA, 2011.
68. T. Wenisch et al. Temporal Streaming of Shared Memory. In ISCA, pages 222-233, 2005. (Pubitemid 41543443)
69. S. C. Woo et al. The SPLASH-2 Programs: Characterization and Methodological Considerations. In ISCA, 1995.
70. D. A. Wood et al. Verifying a multiprocessor cache controller using random case generation. IEEE DToC, 7(4), 1990.
71. J. Zebchuk et al. A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy. In MICRO, pages 314-327, 2007.
72. J. Zebchuk et al. A Tagless Coherence Directory. In MICRO, 2009.