So many states, so little time: Verifying memory coherence in the Cray X1

Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003

Volumn , Issue , 2003, Pages

  Abts, Dennis ^a   Scott, Steve ^a   Lilja, David J ^b  

^a CRAY INC   (United States)

^b UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; DISTRIBUTED PARAMETER NETWORKS; ERRORS;

ARCHITECTURAL MODELING; CACHE COHERENCE PROTOCOLS; COHERENCE PROTOCOL; IMPLEMENTATION ERROR; LOGIC SIMULATIONS; SYSTEM ARCHITECTS; VERIFICATION METHOD; VERIFYING MEMORY COHERENCES;

MODEL CHECKING;

EID: 84947253476     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2003.1213087     Document Type: Conference Paper

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