A framework for coarse-grain optimizations in the on-chip memory hierarchy

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2007, Pages 314-326

  Zebchuk, Jason ^a   Safi, Elham ^a   Moshovos, Andreas ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS PATTERNS; BUILDING BLOCKS; CACHE DESIGNS; CHIP MULTI PROCESSOR (CMP); COHERENCE TRAFFIC; COMMERCIAL TECHNOLOGIES; DATA CAPACITY; FULL SYSTEM SIMULATIONS; INTERNATIONAL SYMPOSIUM; MANAGEMENT STRUCTURES; MEMORY HIERARCHIES; MICRO ARCHITECTURES; MISS RATES; ON CHIP MEMORIES; ON CHIPS; PRE-FETCHING; REDUCTION TECHNIQUES;

CODES (SYMBOLS); COST BENEFIT ANALYSIS; COST REDUCTION; GRAIN (AGRICULTURAL PRODUCT); MULTIPROCESSING SYSTEMS; OPTIMIZATION;

AGRICULTURAL PRODUCTS;

EID: 47349115313     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2007.14     Document Type: Conference Paper

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