Fidelity and scaling of the PARSEC benchmark inputs

IEEE International Symposium on Workload Characterization, IISWC'10

Volumn , Issue , 2010, Pages

  Bienia, Christian ^a   Li, Kai ^a  

^a PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION ERRORS; BENCHMARK SUITES; INPUT SELECTION; INPUT SET; MULTIPLE LEVELS; OPTIMIZATION PROBLEMS; TIME CONSTRAINTS;

EID: 78751484931     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IISWC.2010.5649519     Document Type: Conference Paper

References (26)

1. M. P. Bailey and W. G. Kemple. The Scientific Method of Choosing Model Fidelity. In Proceedings of the 24th Conference on Winter Simulation, pages 791-797, New York, NY, USA, 1992. ACM.
2. C. Bienia, S. Kumar, and K. Li. PARSEC vs. SPLASH-2: A Quantitative Comparison of Two Multithreaded Benchmark Suites on Chip-Multiprocessors. In Proceedings of the 2008 International Symposium on Workload Characterization, September 2008.
3. C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC Benchmark Suite: Characterization and Architectural Implications. In Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, October 2008.
4. P. D. Bryan, M. C. Rosier, and T. M. Conte. Reverse State Reconstruction for Sampled Microarchitectural Simulation. International Symmposium on Performance Analysis of Systems and Software, pages 190-199, 2007.
5. T. Conte, M. Ann, H. Kishore, and N. Menezes. Reducing State Loss For Effective Trace Sampling of Superscalar Processors. In Proceedings of the 1996 International Conference on Computer Design, pages 468-477, 1996.
6. K. Dudzinski and S. Walukiewicz. Exact Methods for the Knapsack Problem and its Generalizations. European Journal of Operations Research, 28(1):3-21, 1987.
7. L. Eeckhout, A. Georges, and K. D. Bosschere. Selecting a Reduced but Representative Workload. In Middleware Benchmarking: Approaches, Results, Experiences. OOSPLA workshop, 2003.
8. L. Eeckhout, S. Nussbaum, J. E. Smith, and K. D. Bosschere. Statistical Simulation: Adding Efficiency to the Computer Designer's Toolbox. IEEE Micro, 23:26-38, 2003.
9. L. Eeckhout, H. Vandierendonck, and K. D. Bosschere. Quantifying the Impact of Input Data Sets on Program Behavior and its Applications. Journal of Instruction-Level Parallelism, 5:1-33, 2003.
10. R. Giladi and N. Ahituv. SPEC as a Performance Evaluation Measure. Computer, 28(8):33-42, 1995.
11. J. Haskins, K. Skadron, A. KleinOsowski, and D. J. Lilja. Techniques for Accurate, Accelerated Processor Simulation: Analysis of Reduced Inputs and Sampling. Technical report, Charlottesville, VA, USA, 2002.
12. J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 2003.
13. A. Joshi, A. Phansalkar, L. Eeckhout, and L. K. John. Measuring Benchmark Similarity Using Inherent Program Characteristics. IEEE Transactions on Computers, 28(8):33-42, 1995.
14. A. KleinOsowski and D. J. Lilja. MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research. Computer Architecture Letters, 1, 2002.
15. R. M. Nauss. The 0-1 Knapsack Problem with Multiple-Choice Constraints. European Journal of Operations Research, 2(2):125-131, 1978.
16. S. Nussbaum and J. E. Smith. Modeling Superscalar Processors via Statistical Simulation. In Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques, pages 15-24, Washington, DC, USA, 2001. IEEE Computer Society.
17. S. Nussbaum and J. E. Smith. Statistical Simulation of Symmetric Multiprocessor Systems. In Proceedings of the 35th Annual Simulation Symposium, page 89, Washington, DC, USA, 2002. IEEE Computer Society.
18. A. Phansalkar, A. Joshi, and L. K. John. Analysis of Redundancy and Application Balance in the SPEC CPU2006 Benchmark Suite. In ISCA '07: Proceedings of the 34th Annual International Symposium on Computer Architecture, pages 412-423,NewYork,NY,USA, 2007.ACM.
19. D. Pisinger. A Minimal Algorithm for the Multiple-Choice Knapsack Problem. European Journal of Operational Research, 83:394-410, 1994.
20. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically Characterizing Large-Scale Program Behavior. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 45-57, New York, NY, USA, 2002. ACM.
21. P. Sinha and A. A. Zoltners. The Multiple-Choice Knapsack Problem. Operations Research, 27(3):503-515, 1979.
22. R. Todi. SPEClite: Using Representative Samples to Reduce SPEC CPU2000 Workload. In Proceedings of the 2001 IEEE International Workshop of Workload Characterization, pages 15-23, Washington, DC, USA, 2001. IEEE Computer Society.
23. Vandierendonck, H. and De Bosschere, K. Many Benchmarks Stress the Same Bottlenecks. In Workshop on Computer Architecture Evaluation Using Commercial Workloads, pages 57-64, 2 2004.
24. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. In Proceedings of the 22nd International Symposium on Computer Architecture, pages 24-36, June 1995.
25. R. E. Wunderlich, T. F. Wenisch, B. Falsafi, and J. C. Hoe. SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling. In Proceedings of the 30th Annual International Symposium on Computer Architecture, pages 84-97, 2003.
26. J. J. Yi, S. V. Kodakara, R. Sendag, D. J. Lilja, and D. M. Hawkins. Characterizing and Comparing Prevailing Simulation Techniques. In Proceedings of the 11th International Symposium on High-Performance Computer Architecture, pages 266-277, Washington, DC, USA, 2005. IEEE Computer Society.