Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2009, Pages 413-422

  Hackenberg, Daniel ^a   Molka, Daniel ^a   Nagel, Wolfgang E ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

Benchmark; Coherency; Multi core; Nehalem; Shanghai

Indexed keywords

ARCHITECTURAL PROPERTIES; BANDWIDTH MEASUREMENTS; CACHE ARCHITECTURE; CACHE COHERENCY PROTOCOL; CC-NUMA; INTEGRATED MEMORY CONTROLLERS; MEMORY PERFORMANCE; MEMORY SUBSYSTEMS; MULTI CORE; MULTI PROCESSOR SYSTEMS; MULTICORE TECHNOLOGY; OPTIMAL APPLICATIONS; PERFORMANCE IMPACT; PERFORMANCE IMPROVEMENTS;

MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; SHAPE MEMORY EFFECT;

CACHE MEMORY;

EID: 76749126627     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1669112.1669165     Document Type: Conference Paper

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