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Volumn 30, Issue 5, 2010, Pages 54-65

SARC coherence: Scaling directory cache coherence in performance and power

Author keywords

[No Author keywords available]

Indexed keywords

CACHE COHERENCE; COHERENCE PROTOCOL; POWER SCALABILITY; SHARED MEMORIES;

EID: 78649527148     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2010.82     Document Type: Article
Times cited : (55)

References (9)
  • 1
    • 0002085747 scopus 로고
    • What is scalability?
    • M. Hill, "What is Scalability?" Computer Architecture News, vol. 18, no. 4, 1990, pp. 18-21.
    • (1990) Computer Architecture News , vol.18 , Issue.4 , pp. 18-21
    • Hill, M.1
  • 3
    • 78649506751 scopus 로고    scopus 로고
    • The SARC architecture
    • A. Ramirez et al., "The SARC Architecture", IEEE Micro, vol. 30, no. 5, 2010, pp. 16-29.
    • (2010) IEEE Micro , vol.30 , Issue.5 , pp. 16-29
    • Ramirez, A.1
  • 4
    • 0026839484 scopus 로고
    • The stanford DASH multiprocessor
    • D. Lenoski et al., "The Stanford DASH Multiprocessor", Computer, vol. 25, no. 3, 1992, pp. 63-79.
    • (1992) Computer , vol.25 , Issue.3 , pp. 63-79
    • Lenoski, D.1
  • 5
    • 0029202473 scopus 로고
    • Dynamic self-invalidation: Reducing coherence overhead in shared-memory multiprocessors
    • IEEE Press
    • A. R. Lebeck and D. Wood, "Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors", Proc. Int'l Symp. Computer Architecture (ISCA-22), IEEE Press, 1995, pp. 48-59.
    • (1995) Proc. Int'l Symp. Computer Architecture (ISCA-22) , pp. 48-59
    • Lebeck, A.R.1    Wood, D.2
  • 6
    • 0012693415 scopus 로고
    • Programming for different memory consistency models
    • K. Gharachorloo et al., "Programming for Different Memory Consistency Models", J. Parallel and Distributed Computing, vol. 15, no. 4, 1992, pp. 399-407.
    • (1992) J. Parallel and Distributed Computing , vol.15 , Issue.4 , pp. 399-407
    • Gharachorloo, K.1
  • 7
    • 84876572683 scopus 로고    scopus 로고
    • Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture
    • IEEE Press
    • M. E. Acacio et al., "Owner Prediction for Accelerating Cache-to-Cache Transfer Misses in a cc-NUMA Architecture", Proc. Int'l Conf. Supercomputing (ICS-02), IEEE Press, 2002, pp. 1-12.
    • (2002) Proc. Int'l Conf. Supercomputing (ICS-02) , pp. 1-12
    • Acacio, M.E.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.