-
1
-
-
0011732087
-
RF-SoC - Expectations and required conditions
-
Mar
-
A. Matsuzawa, "RF-SoC - Expectations and required conditions," IEEE Trans. Microwave Theory Tech., vol. 50, pp. 245-253, Mar. 2002.
-
(2002)
IEEE Trans. Microwave Theory Tech.
, vol.50
, pp. 245-253
-
-
Matsuzawa, A.1
-
2
-
-
0016943318
-
GaAs microwave power FET
-
M. Fukuta, K. Suyama, H. Suzuki, and H. Ishikawa, "GaAs microwave power FET," IEEE Trans. Electron Devices, vol. ED-23, pp. 388-394, 1976.
-
(1976)
IEEE Trans. Electron Devices
, vol.ED-23
, pp. 388-394
-
-
Fukuta, M.1
Suyama, K.2
Suzuki, H.3
Ishikawa, H.4
-
3
-
-
0019578938
-
Design considerations for monolithic microwave circuits
-
Apr
-
R. A. Pucel, "Design considerations for monolithic microwave circuits," IEEE Trans. Microwave Theory Tech., vol. MTT-29, pp. 513-534, Apr., 1981.
-
(1981)
IEEE Trans. Microwave Theory Tech.
, vol.MTT-29
, pp. 513-534
-
-
Pucel, R.A.1
-
4
-
-
0032307449
-
A novel fabrication process for surface via-holes for GaAs power FETs
-
H. Furukawa, T. Fukui, T. Tanaka, A. Noma, and D. Ueda, "A novel fabrication process for surface via-holes for GaAs power FETs," in Proc. IEEE GaAs Conf., 1998, pp. 251-254.
-
(1998)
Proc. IEEE GaAs Conf.
, pp. 251-254
-
-
Furukawa, H.1
Fukui, T.2
Tanaka, T.3
Noma, A.4
Ueda, D.5
-
5
-
-
0028125418
-
Fabrication technology for wafer through-hole interconnections and three-dimensional stacks of chips and wafers
-
S. Linder, H. Baltes, F. Gnaedinger, and E. Doering, "Fabrication technology for wafer through-hole interconnections and three-dimensional stacks of chips and wafers," in Proc. MEMS, 1994, pp. 349-354.
-
(1994)
Proc. MEMS
, pp. 349-354
-
-
Linder, S.1
Baltes, H.2
Gnaedinger, F.3
Doering, E.4
-
6
-
-
0034454824
-
A micromachining post-process module for RF silicon technology
-
N. P. Pham, K. T. Ng, M. Bartek, P. M. Sarro, B. Rejaei, and J. N. Burghartz, "A micromachining post-process module for RF silicon technology," in IEDM Tech. Dig., 2000, pp. 481-484.
-
(2000)
IEDM Tech. Dig.
, pp. 481-484
-
-
Pham, N.P.1
Ng, K.T.2
Bartek, M.3
Sarro, P.M.4
Rejaei, B.5
Burghartz, J.N.6
-
7
-
-
0038493949
-
High aspect ratio through-wafer interconnections for 3-D microsystems
-
L. Wang, A. Nichelatti, H. Schellevis, C. de Boer, C. Visser, T. N. Nguyen, and P. M. Sarro, "High aspect ratio through-wafer interconnections for 3-D microsystems," in Proc. MEMS, 2003, pp. 634-637.
-
(2003)
Proc. MEMS
, pp. 634-637
-
-
Wang, L.1
Nichelatti, A.2
Schellevis, H.3
de Boer, C.4
Visser, C.5
Nguyen, T.N.6
Sarro, P.M.7
-
8
-
-
0141918454
-
The importance of distributed grounding in combination with porous Si trenches for the reduction of RF crosstalk through p- Si substrate
-
June
-
H. S. Kim, K. Chong, Y.-H. Xie, and K. A. Jenkins, "The importance of distributed grounding in combination with porous Si trenches for the reduction of RF crosstalk through p- Si substrate," IEEE Electron Device Lett., vol. 24, pp. 640-642, June 2003.
-
(2003)
IEEE Electron Device Lett.
, vol.24
, pp. 640-642
-
-
Kim, H.S.1
Chong, K.2
Xie, Y.-H.3
Jenkins, K.A.4
-
9
-
-
0342393889
-
Ultra-low resistance, through-wafer via (TWV) technology and its applications in three dimensional structures in silicon
-
H. T. Soh, C. P. Yue, A. M. McCarthy, C. Ryu, T. H. Lee, and C. F. Quate, "Ultra-low resistance, through-wafer via (TWV) technology and its applications in three dimensional structures in silicon," in Proc. Int. Conf. Solid State Devices Materials, 1998, pp. 284-285.
-
(1998)
Proc. Int. Conf. Solid State Devices Materials
, pp. 284-285
-
-
Soh, H.T.1
Yue, C.P.2
McCarthy, A.M.3
Ryu, C.4
Lee, T.H.5
Quate, C.F.6
-
10
-
-
0033361875
-
Via hole technology for microstrip transmission lines and passive elements on high resistivity silicon
-
K. M. Strohm, P. Nuechter, C. N. Rheinfelder, and R. Guehl, "Via hole technology for microstrip transmission lines and passive elements on high resistivity silicon," in Proc. IEEE MTT-S Int. Microwave Symp., 1999, pp. 581-584.
-
(1999)
Proc. IEEE MTT-S Int. Microwave Symp.
, pp. 581-584
-
-
Strohm, K.M.1
Nuechter, P.2
Rheinfelder, C.N.3
Guehl, R.4
-
11
-
-
0036904516
-
Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates
-
E. M. Chow, V. Chandrasekaran, A. Partridge, T. Nishida, M. Sheplak, C. F. Quate, and T. W. Kenny, "Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates," J. Microelectromech. Syst., vol. 11, pp. 631-640, 2002.
-
(2002)
J. Microelectromech. Syst.
, vol.11
, pp. 631-640
-
-
Chow, E.M.1
Chandrasekaran, V.2
Partridge, A.3
Nishida, T.4
Sheplak, M.5
Quate, C.F.6
Kenny, T.W.7
-
12
-
-
0000510384
-
A Faraday cage isolation structure for substrate crosstalk suppression
-
May
-
J. H. Wu, J. Scholvin, J. A. del Alamo, and K. A. Jenkins, "A Faraday cage isolation structure for substrate crosstalk suppression," IEEE Microwave Wireless Comp. Lett., vol. 11, pp. 410-412, May 2001.
-
(2001)
IEEE Microwave Wireless Comp. Lett.
, vol.11
, pp. 410-412
-
-
Wu, J.H.1
Scholvin, J.2
del Alamo, J.A.3
Jenkins, K.A.4
-
13
-
-
0035446333
-
An insulator-lined silicon substrate-via technology with high aspect ratio
-
Dec
-
J. H. Wu, J. Scholvin, and J. A. del Alamo, "An insulator-lined silicon substrate-via technology with high aspect ratio," IEEE Trans. Electron Devices, vol. 48, pp. 2181-2183, Dec. 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, pp. 2181-2183
-
-
Wu, J.H.1
Scholvin, J.2
del Alamo, J.A.3
-
14
-
-
0032753082
-
Characterization of a time multiplexed inductively coupled plasma etcher
-
A. A. Ayón, R. Braff, C. C. Lin, H. H. Sawin, and M. A. Schmidt, "Characterization of a time multiplexed inductively coupled plasma etcher," J. Electrochem. Soc., vol. 146, pp. 339-349, 1999.
-
(1999)
J. Electrochem. Soc.
, vol.146
, pp. 339-349
-
-
Ayón, A.A.1
Braff, R.2
Lin, C.C.3
Sawin, H.H.4
Schmidt, M.A.5
-
15
-
-
84975340255
-
Reliability of copper metallization on silicon-dioxide
-
Y. Shacham-Diamand, A. Dedhia, D. Hoffstetter, and W. G. Oldham, "Reliability of copper metallization on silicon-dioxide," in Proc. Int. IEEE VLSI Multilevel Interconnection Conf., 1991, pp. 109-115.
-
(1991)
Proc. Int. IEEE VLSI Multilevel Interconnection Conf.
, pp. 109-115
-
-
Shacham-Diamand, Y.1
Dedhia, A.2
Hoffstetter, D.3
Oldham, W.G.4
-
16
-
-
0027543093
-
Passivation schemes for copper/polymer thin-film interconnections used in multichip modules
-
Jan
-
G. M. Adema, L.-T. Hwang, G. A. Rinne, and I. Turlik, "Passivation schemes for copper/polymer thin-film interconnections used in multichip modules," IEEE Trans. Comp., Hybrids, Manufact. Technol., vol. 16, pp. 53-59, Jan. 1993.
-
(1993)
IEEE Trans. Comp., Hybrids, Manufact. Technol.
, vol.16
, pp. 53-59
-
-
Adema, G.M.1
Hwang, L.-T.2
Rinne, G.A.3
Turlik, I.4
-
17
-
-
0025529974
-
Advantages of dual frequency PECVD for deposition of ILD and passivation films
-
E. P. van de Ven, I.-W. Connick, and A. S. Harrus, "Advantages of dual frequency PECVD for deposition of ILD and passivation films," in Proc. Int. IEEE VLSI Multilevel Interconnection Conf., 1990, pp. 194-201.
-
(1990)
Proc. Int. IEEE VLSI Multilevel Interconnection Conf.
, pp. 194-201
-
-
van de Ven, E.P.1
Connick, I.-W.2
Harrus, A.S.3
-
18
-
-
0031695978
-
Copper interconnections and reliability
-
C.-K. Hu and J. M. E. Harper, "Copper interconnections and reliability," Mater. Chem. Phys., vol. 52, pp. 5-16, 1998.
-
(1998)
Mater. Chem. Phys.
, vol.52
, pp. 5-16
-
-
Hu, C.-K.1
Harper, J.M.E.2
-
19
-
-
0019601433
-
Forming electrical interconnections through semiconductor wafers
-
T. R. Anthony, "Forming electrical interconnections through semiconductor wafers," J. Appl. Phys., vol. 52, pp. 5340-5349, 1981.
-
(1981)
J. Appl. Phys.
, vol.52
, pp. 5340-5349
-
-
Anthony, T.R.1
-
21
-
-
0036441806
-
On-chip RF isolation techniques
-
T. Blalack, Y. Leclercq, and C. P. Yue, "On-chip RF isolation techniques," in Proc. IEEE BCTM, 2002, pp. 205-211.
-
(2002)
Proc. IEEE BCTM
, pp. 205-211
-
-
Blalack, T.1
Leclercq, Y.2
Yue, C.P.3
-
22
-
-
0029507118
-
Signal isolation in BICMOS mixed mode integrated circuits
-
K. Joardar, "Signal isolation in BICMOS mixed mode integrated circuits," in Proc. IEEE BCTM, 1995, pp. 178-181.
-
(1995)
Proc. IEEE BCTM
, pp. 178-181
-
-
Joardar, K.1
-
23
-
-
41549122718
-
Comparison of SOI versus bulk silicon substrate crosstalk properties for mixed-mode ICs
-
I. Rahim, B.-Y. Hwang, and J. Foerstner, "Comparison of SOI versus bulk silicon substrate crosstalk properties for mixed-mode ICs," in Proc. IEEE Int. SOI Conf., 1992, pp. 170-171.
-
(1992)
Proc. IEEE Int. SOI Conf.
, pp. 170-171
-
-
Rahim, I.1
Hwang, B.-Y.2
Foerstner, J.3
-
24
-
-
0031341419
-
Substrate crosstalk reduction using SOI technology
-
Dec
-
J.-P. Raskin, A. Viviani, D. Flandre, and J.-P. Colinge, "Substrate crosstalk reduction using SOI technology," IEEE Trans. Electron Devices, vol. 44, pp. 2252-2261, Dec. 1997.
-
(1997)
IEEE Trans. Electron Devices
, vol.44
, pp. 2252-2261
-
-
Raskin, J.-P.1
Viviani, A.2
Flandre, D.3
Colinge, J.-P.4
-
25
-
-
1642306308
-
Ultralow silicon substrate noise crosstalk using metal Faraday cages in an SOI technology
-
Mar
-
S. Stefanou, J. S. Hamel, P. Baine, M. Bain, B. M. Armstrong, H. S. Gamble, M. Kraft, and H. A. Kemhadjian, "Ultralow silicon substrate noise crosstalk using metal Faraday cages in an SOI technology," IEEE Trans. Electron Devices, vol. 51, pp. 486-491, Mar. 2004.
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, pp. 486-491
-
-
Stefanou, S.1
Hamel, J.S.2
Baine, P.3
Bain, M.4
Armstrong, B.M.5
Gamble, H.S.6
Kraft, M.7
Kemhadjian, H.A.8
-
26
-
-
4444339051
-
An equivalent circuit model for a Faraday cage substrate crosstalk isolation structure
-
J. H. Wu and J. A. del Alamo, "An equivalent circuit model for a Faraday cage substrate crosstalk isolation structure," in Proc. IEEE Radio Frequency Integrated Circuits Symp., 2004, pp. 635-638.
-
(2004)
Proc. IEEE Radio Frequency Integrated Circuits Symp.
, pp. 635-638
-
-
Wu, J.H.1
del Alamo, J.A.2
|