On-chip RF isolation techniques

Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting

Volumn , Issue , 2002, Pages 205-211

  Blalack, Tallis ^a   Leclercq, Youri ^a   Yue, C Patrick ^b  

^a CADENCE DESIGN SYSTEMS   (United States)

^b Atheros Communications   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DOPING (ADDITIVES); ELECTRIC GROUNDING; ELECTRIC IMPEDANCE; ELECTRIC SHIELDING; FABRICATION;

CAPACITIVE DECOUPLING;

MICROPROCESSOR CHIPS;

EID: 0036441806     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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