Novel fabrication process of surface via-holes for GaAs power FETs

Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)

Volumn , Issue , 1998, Pages 251-254

  Furukawa, Hidetoshi ^a   Fukui, Takeshi ^a   Tanaka, Tsuyoshi ^a   Noma, Atsushi ^a   Ueda, Daisuke ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTROPLATING; ETCHING; SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTOR DEVICE MANUFACTURE;

SURFACE VIA-HOLE (SVH);

FIELD EFFECT TRANSISTORS;

EID: 0032307449     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)