Scalable hybrid wireless network-on-chip architectures for multicore systems

IEEE Transactions on Computers

Volumn 60, Issue 10, 2011, Pages 1485-1502

  Ganguly, Amlan ^a   Chang, Kevin ^b   Deb, Sujay ^b   Pande, Partha Pratim ^b   Belzer, Benjamin ^b   Teuscher, Christof ^c  

^a Rochester Institute of Technology   (United States)

^b Washington State University   (United States)

^c Department of Electrical and Computer Engineering   (United States)

Author keywords

multicore; Network on chip; on chip antenna; small world network; wireless communication

Indexed keywords

MULTI CORE; NETWORK ON CHIP; ON CHIP ANTENNA; SMALL WORLD NETWORKS; WIRELESS COMMUNICATION;

ANTENNAS; ENERGY DISSIPATION; INNOVATION; NETWORK ARCHITECTURE; SERVERS; TECHNOLOGY; VLSI CIRCUITS; WIRELESS TELECOMMUNICATION SYSTEMS;

WIRELESS NETWORKS;

EID: 80052624932     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2010.176     Document Type: Article

References (46)

1. L. Benini and G.D. Micheli, "Networks on Chips: A New SoC Paradigm," Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
2. U.Y. Ogras and R. Marculescu, "It's a Small World After All: NoC Performance Optimization via Long-Range Link Insertion," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 14, no. 7, pp. 693-706, July 2006.
3. A. Kumar et al., "Toward Ideal On-Chip Communication Using Express Virtual Channels," IEEE Micro, vol. 28, no. 1, pp. 80-90, Jan.-Feb. 2008.
4. T. Krishna et al., "NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication," Proc. IEEE Symp. High Performance Interconnects (HOTI), pp. 11-20, Aug. 2008.
5. ITRS, http://www.itrs.net/Links/2007ITRS/Home2007.htm, 2007.
6. V.F. Pavlidis and E.G. Friedman, "3D Topologies for Networkson- Chip," IEEE Trans. Very Large Scale Integration (VLSI) Sysrems, vol. 15, no 10, pp. 1081-1090, Oct. 2007.
7. A. Shacham et al., "Photonic Network-on-Chip for Future Generations of Chip Multi-Processors," IEEE Trans. Computers, vol. 57, no. 9, pp. 1246-1260, 2008.
8. M.F. Chang et al., "CMP Network-on-Chip Overlaid with Multi- Band RF-Interconnect," Proc. IEEE Int'l Symp. High-Performance Computer Architecture (HPCA), pp. 191-202, Feb. 2008.
9. J. Lin et al., "Communication Using Antennas Fabricated in Silicon Integrated Circuits," IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1678-1687, Aug. 2007.
10. P.J. Burke et al., "Quantitative Theory of Nanowire and Nanotube Antenna Performance," IEEE Trans. Nanotechnology, vol. 5, no. 4, pp. 314-334, July 2006.
11. K. Kempa et al., "Carbon Nanotubes as Optical Antennae," Advanced Materials, vol. 19, pp. 421-426, 2007.
12. K.K O et al., "The Feasibility of On-Chip Interconnection Using Antennas," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD '05), pp. 979-984, 2005.
13. D.J. Watts, Small Worlds: The Dynamics of Networks between Order and Randomness, Princeton Univ. Press, 1999.
14. B. Feero and P.P. Pande, "Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation," IEEE Trans. Computers, vol. 58, no. 1, pp. 32-45, Jan. 2009.
15. D. Park et al., "MIRA: A Multi-Layered On-Chip Interconnect Router Architecture," IEEE Int'l Symp. Computer Architecture (ISCA), pp. 251-261, June 2008.
16. W.R. Davis et al., "Demystifying 3D ICs: The Pros and Cons of Going Vertical," IEEE Design and Test of Computers, vol. 22, no 6, pp. 498-510, Nov.-Dec. 2005.
17. A.W. Topol et al., "Three-Dimensional Integrated Circuits," IBM J. Research & Development, vol. 50, nos. 4/5, pp. 491-506, July/Sept. 2006.
18. A.P. Jose et al., "Pulsed Current-Mode Signaling for Nearly Speedof- Light Intrachip Communication," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 772-780, Apr. 2006.
19. R.T. Chang et al., "Near Speed-of-Light Signaling over On-Chip Electrical Interconnects," IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 834-838, May 2003.
20. I. O'Connor et al., "Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 15, no. 8, pp. 927-940, Aug. 2007.
21. M. Briere et al., "System Level Assessment of an Optical NoC in an MPSoC Platform," Proc. IEEE Design, Automation and Test in Europe Conf. and Exhibition, pp-1084-1089, Apr. 2007.
22. M.F. Chang et al., "RF Interconnects for Communications On- Chip," Proc. Int'l Symp. Physical Design, pp. 78-83, Apr. 2008.
23. B.A. Floyd et al., "Intra-Chip Wireless Interconnect for Clock Distribution Implemented with Integrated Antennas, Receivers, and Transmitters," IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 543-552, May 2002.
24. D. Zhao and Y. Wang, "SD-MAC: Design and Synthesis of a Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip," IEEE Trans. Computers, vol. 57, no. 9, pp. 1230-1245, Sept. 2008.
25. R. Albert and A.-L. Barabasi, "Statistical Mechanics of Complex Networks," Rev. of Modern Physics, vol. 74, pp. 47-97, Jan. 2002.
26. M. Buchanan, Nexus: Small Worlds and the Groundbreaking Theory of Networks. Norton, W. W. & Company, 2003.
27. C. Teuscher, "Nature-Inspired Interconnects for Self-Assembled Large-Scale Network-on-Chip Designs," Chaos, vol. 17, no. 2, 2007.
28. D.J. Watts and S.H. Strogatz, "Collective Dynamics of 'Small- World' Networks," Nature, vol. 393, pp. 440-442, 1998.
29. T. Petermann and P. De Los Rios, "Physical Realizability of Small- World Networks," Physical Rev. E, vol. 73, 2006.
30. S. Kirkpatrick et al., "Optimization by Simulated Annealing," Science, vol. 220, pp. 671-680, 1983.
31. J. Duato et al., Interconnection Networks-An Engineering Approach. Morgan Kaufmann Publishers, 2002.
32. M. Fukuda et al., "A 0.18 μm CMOS Impulse Radio Based UWB Transmitter for Global Wireless Interconnections of 3D Stacked- Chip System," Proc. Int'l Conf. Solid State Devices and Materials, pp. 72-73, Sept. 2006.
33. G.W. Hanson, "On the Applicability of the Surface Impedance Integral Equation for Optical and Near Infrared Copper Dipole Antennas," IEEE Trans. Antennas and Propagation, vol. 54, no. 12, pp. 3677-3685, Dec. 2006.
34. Y. Huang et al., "Performance Prediction of Carbon Nanotube Bundle Dipole Antennas," IEEE Trans. Nanotechnology, vol. 7, no. 3, pp. 331-337, May 2008.
35. Y. Zhou et al., "Design and Fabrication of Microheaters for Localized Carbon Nanotube Growth" Proc. IEEE Conf. Nanotechnology, pp. 452-455, 2008.
36. M. Freitag et al., "Hot Carrier Electroluminescence from a Single Carbon Nanotube," Nano Letters, vol. 4, no. 6, pp. 1063-1066, 2004.
37. T.S. Marinis et al., "Wafer Level Vacuum Packaging of MEMS Sensors," Proc. Electronic Components and Technology Conf., vol. 2, pp. 1081-1088, May-June 2005.
38. B.G. Lee et al., "Ultrahigh-Bandwidth Silicon Photonic Nanowire Waveguides for On-Chip Networks," IEEE Photonics Technology Letters, vol. 20, no. 6, pp. 398-400, Mar. 2008.
39. W.M.J. Green et al., "Ultra-Compact, Low RF Power, 10Gb/s Silicon Mach-Zehnder Modulator," Optics Express, vol. 15, no. 25, pp. 17106-17113, 2007.
40. Z. Lu et al., "Connection-Oriented Multicasting in Wormhole- Switched Networks on Chip," Proc. IEEE CS Ann. Symp. VLSI: Emerging VLSI Technologies and Architectures, pp. 205-210, 2006.
41. P.P. Pande et al., "Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures," IEEE Trans. Computers, vol. 54, no. 8, pp. 1025-1040, Aug. 2005.
42. A. Ismail and A. Abidi, "A 3 to 10 GHz LNA Using a Wideband LC-Ladder Matching Network," Proc. IEEE Int'l Solid-State Circuits Conf., pp. 384-534, Feb. 2004.
43. Circuits Multi-Projects, http://cmp.imag.fr, 2010.
44. E. Mensink et al., "A 0.28pf/b 2gb/s/ch Transceiver in 90 nm CMOS for 10 mm On-Chip Interconnects," Proc. IEEE Solid-State Circuits Conf., pp. 412-413, Feb. 2007.
45. D. Vantrease et al., "Corona: System Implications of Emerging Nanophotonic Technology," Proc. IEEE Int'l Symp. Computer Architecture (ISCA), pp. 153-164, June 2008.
46. P. Bogdan and R. Marculescu, "Quantum-Like Effects in Networkon- Chip Buffers Behavior," Proc. IEEE Design Automation Conf. (DAC), pp. 266-267, June 2007.