A 0.28pJ/b 2Gb/s/ch transceiver in 90nm CMOS for 10mm on-chip interconnects

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 414-416

  Mensink, Eisse ^a   Schinkel, Daniël ^a   Klumperink, Eric ^a   Van Tuijl, Ed ^a   Nauta, Bram ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CHIP SCALE PACKAGES; INTERCONNECTION NETWORKS; NANOELECTRONICS; TRANSCEIVERS;

CONTINUOUS TIME FEEDBACK FILTERS; FEEDBACK FILTERS; ON CHIP INTERCONNECTS;

CMOS INTEGRATED CIRCUITS;

EID: 34548833578     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373470     Document Type: Conference Paper

References (6)

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2. A. P. Jose, G. Patounakis, and K. L. Shepard, "Pulsed Current-Mode Signaling for Nearly Speed-of-Light Intrachip Communication," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 772-780, Apr., 2006.
3. A. P. Jose, and K. L. Shepard, "Distributed Loss Compensation for Low-Latency On-Chip Interconnects," ISSCC Dig. Tech. Papers, pp. 516517, Feb., 2006.
4. L. Zhang, J. Wilson, R. Bashirullah, et al, "Driver Pre-Emphasis Techniques for On-Chip Global Buses," ISLPED, pp. 186-191, Aug., 2005.
5. H. Zhang, V. George, and J. M. Rabaey; "Low-Swing On-Chip Signaling Techniques: Effectiveness and Robustness," IEEE Trans. VLSI Systems, vol. 8, pp. 2, 64-272, Jun., 2000.
6. V. Stojanovic, A. Ho, B. Garlepp, et al., "Adaptive, Equalization and Data Recovery in a Dual-Mode (PAM2/4) Serial, Link Transceiver," Symp. VLSI Circuits, pp. 348-351. Jun., 2004.