Pulsed current-mode signaling for nearly speed-of-light intrachip communication

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 4, 2006, Pages 772-780

  Jose, Anup P ^a,b,c,d   Patounakis, George ^a,b   Shepard, Kenneth L ^a,b  

^a IEEE   (United States)

^b Department of Earth and Environmental Sciences   (United States)

^c AMD Boston Design Center   (United States)

^d Boston Design Center AMD   (United States)

Author keywords

High speed integrated circuits; Integrated circuit interconnections; On chip communication; Serial links; Transmission lines

Indexed keywords

HIGH-SPEED INTEGRATED CIRCUITS; INTEGRATED CIRCUIT INTERCONNECTIONS; ON-CHIP COMMUNICATION; SERIAL LINKS;

DATA COMMUNICATION SYSTEMS; ELECTRIC LINES; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS;

SIGNALING;

EID: 33645654262     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.870922     Document Type: Conference Paper

References (14)

1. R. Ho, K. W. Mai, and M. A. Horowitz, "The future of wires," Proc. IEEE, vol. 89, no. 4, pp. 490-504, Apr. 2001.
2. P Saxena, N. Menezes, P. Cocchini, and D. A. Kirkpatrick, "The scaling challenge: can correct-by-construction design help?," in Proc. Int. Symp. Physical Design, 2003, pp. 51-57.
3. C. Kim, D. Burger, and S. W. Keckler, "Nonuniform cache architectures for wire-delay dominated on-chip caches," IEEE Micro, vol. 23, no. 6, pp. 99-107, Nov-Dec. 2003.
4. R. T. Chang, N. Talwalkar, C. P. Yue, and S. S. Wong, "Near speed-of-light signaling over on-chip electrical interconnects," IEEE J. Solid-State Cil-cuits, vol. 34, no. 5, pp. 834-838, May 2003.
5. R. Farjad-Rad, C.-K. K. Yang, M. A. Horowitz, and T. H. Lee, "A 0.4-μmCMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 580-585, May 1999.
6. H. Johnson and M. Graham, High-Speed Digital Design: A Handbook of Black Magic. Englewood Cliffs, NJ: Prentice-Hall, 1993.
7. I. L. W. Couch, Digital and Analog Communication Systems. Englewood Cliffs, NJ: Prentice-Hall, 2001.
8. M.-J. E. Lee, W. J. Dally, and P. Chiang, "Low-power area-efficient high-speed I/O circuit techniques," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1591-1599, Nov. 2000.
9. J. Montanaro et al., "A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1703-1712, Nov. 1996.
10. D.G. Messerschmitt, "Synchronization in digital system design," IEEE J. Sel. Areas Commun., vol. 8, no. 8, pp. 1404-1419, Oct. 1990.
11. S. Sidiropoulos, D. Liu, J. Kim, G. Wei, and M. A. Horowitz, "Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers," in Symp. VLSI Circuits Dig. Tech. Papers, 2000, pp. 124-127.
12. J. G. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996.
13. W. J. Dally and B. Towles, "Route packets, not wires: on-chip interconnection networks," in Proc. Design Automation Conf., 2001, pp. 684-689.
14. H.-S. Wang, L.-S. Peh, and S. Malik, "Power-driven design of router microarchitectures in on-chip networks," in Proc. Int. Symp. Microarchitecture (MICRO), Nov. 2003, pp. 105-116.