Power gating aware task scheduling in MPSoC

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 10, 2011, Pages 1801-1812

  Wang, Yu ^a   Xu, Jiang ^b   Xu, Yan ^a   Liu, Weichen ^b   Yang, Huazhong ^a  

^a TSINGHUA UNIVERSITY   (China)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Mixed integer linear programming (MILP); multiprocessor system on chip (MPSoC); power gating; power ground (P G) noise; task scheduling

Indexed keywords

MIXED-INTEGER LINEAR PROGRAMMING; MULTIPROCESSOR SYSTEM ON CHIPS; POWER GATINGS; POWER GROUND (P/G) NOISE; TASK-SCHEDULING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; HEURISTIC ALGORITHMS; HEURISTIC METHODS; IMAGE CODING; INTEGER PROGRAMMING; MULTIPROCESSING SYSTEMS; MULTITASKING; PROGRAMMABLE LOGIC CONTROLLERS; RELIABILITY; SCHEDULING ALGORITHMS; SIMULATED ANNEALING;

MICROPROCESSOR CHIPS;

EID: 80051790404     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2055907     Document Type: Article

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