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Volumn , Issue , 2008, Pages 146-147

A sub-μs wake-up time power gating technique with bypass power line for rush current support

Author keywords

Power gating; Stand by leakage; Wake up time and rush current noise

Indexed keywords

VLSI CIRCUITS;

EID: 51949101368     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4585984     Document Type: Conference Paper
Times cited : (13)

References (3)
  • 1
    • 28144444694 scopus 로고    scopus 로고
    • 90nm Low Leakage SoC Design Techniques for Wireless Applications
    • Feb
    • P. Royannez and et al., "90nm Low Leakage SoC Design Techniques for Wireless Applications," ISSCC Dig. Tech. Papers, pp. 138-139, Feb., 2005.
    • (2005) ISSCC Dig. Tech. Papers , pp. 138-139
    • Royannez, P.1    and et, al.2
  • 2
    • 39749165816 scopus 로고    scopus 로고
    • A 1.92μs-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors
    • June
    • K. Fukuoka and et al., "A 1.92μs-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors," Dig. Symp. VLSI Circuits, pp. 128-129, June 2007.
    • (2007) Dig. Symp. VLSI Circuits , pp. 128-129
    • Fukuoka, K.1    and et, al.2
  • 3
    • 34548840800 scopus 로고    scopus 로고
    • On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications
    • Feb
    • T. Sato and et al., "On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications," ISSCC Digest of Technical Papers, pp. 290-291, Feb., 2007.
    • (2007) ISSCC Digest of Technical Papers , pp. 290-291
    • Sato, T.1    and et, al.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.