A power gating scheme for ground bounce reduction during mode transition

2007 IEEE International Conference on Computer Design, ICCD 2007

Volumn , Issue , 2007, Pages 388-394

  He, Ku ^a   Luo, Rong ^a   Wang, Yu ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CONSERVATION; EFFICIENCY; ENERGY POLICY; NETWORKS (CIRCUITS); REDUCTION;

COMPUTER DESIGNS; ENERGY CONSUMPTION; GROUND BOUNCE; INTERMEDIATE STATES; INTERNATIONAL CONFERENCES; LEAKAGE POWER; MODE TRANSITIONS; PEAK CURRENTS; PEAK VOLTAGE; POWER GATING; SLEEP MODES; SMALL SIZE; TIME REDUCTION;

ENERGY EFFICIENCY;

EID: 52949100980     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2007.4601929     Document Type: Conference Paper

References (11)

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8. S. Narendra, A. Chandrakasan, Leakage in nanometer CMOS technologies, Springer, 2005.
9. Y. Chang, S. K. Gupta, and M. A. Breuer. "Analysis of ground Bounce in Deep Sub-micron Circuits", Proc. VLSI Test Symposium, 1997, pp. 110-116.
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