A unified methodology for power supply noise reduction in modern microarchitecture design

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2008, Pages 611-616

  Healy, Michael ^a   Mohamood, Fayez ^a   Lee, Hsien Hsin S ^a   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE-CASE; CURRENT CONSUMPTIONS; DECAP ALLOCATION; DESIGN AUTOMATION CONFERENCE; DYNAMIC CONTROLLERS; FLOOR-PLANNING; HIGH FREQUENCY POWER SUPPLY; MICRO-ARCHITECTURE DESIGN; NOISE BEHAVIOR; NOISE CONTROLLED; NOVEL DESIGN METHODOLOGY; POWER SUPPLY NOISE REDUCTION; RUN-TIME; SOUTH PACIFIC; WORST-CASE NOISE;

ACTIVE FILTERS; COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER DISTRIBUTION; ELECTRIC POWER UTILIZATION; ENVIRONMENTAL ENGINEERING; INDUSTRIAL ENGINEERING; NOISE ABATEMENT;

ELECTRIC POWER TRANSMISSION NETWORKS;

EID: 49549122174     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2008.4484024     Document Type: Conference Paper

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