Understanding and minimizing ground bounce during mode transition of power gating structures

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 22-25

  Kim, S ^a   Kosonocky, S V ^a   Knebel, D R ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Circuit noise; Circuit simulation; Clocks; Integrated circuit noise; Permission; Power system reliability; Power systems; Switches; System on a chip; Voltage

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CLOCKS; ELECTRIC POTENTIAL; LOW POWER ELECTRONICS; NOISE ABATEMENT; POWER ELECTRONICS; STANDBY POWER SYSTEMS; SWITCHES; SYSTEM-ON-CHIP; TRANSISTORS;

CIRCUIT NOISE; INTEGRATED CIRCUIT NOISE; PERMISSION; POWER SYSTEM RELIABILITY; SYSTEM ON A CHIP;

CIRCUIT SIMULATION;

EID: 1542329520     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231828     Document Type: Conference Paper

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