Temperature-aware MPSoC scheduling for reducing hot spots and gradients

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2008, Pages 49-54

  Coskun, Ayse Kivilcim ^a   Rosing, Tajana Simunic ^a   Whisnant, Keith A ^b   Gross, Kenny C ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN AUTOMATION CONFERENCE; ENERGY BALANCING; ENERGY MINIMIZATIONS; HOT SPOTTING; INTEGER LINEAR PROGRAMMING; MULTI-PROCESSOR SYSTEMS; OPTIMAL SCHEDULING; PERFORMANCE CONSTRAINTS; RELIABLE SYSTEMS; RUN-TIME; SOUTH PACIFIC; TASK SCHEDULING PROBLEMS; TEMPERATURE GRADIENTS; WORKLOAD VARIATIONS;

COMPUTER AIDED DESIGN; DIES; DIGITAL INTEGRATED CIRCUITS; GRADIENT METHODS; INDUSTRIAL ENGINEERING; INTEGER PROGRAMMING; LINEARIZATION; MULTIPROCESSING SYSTEMS; OPTIMIZATION; SCHEDULING;

LINEAR PROGRAMMING;

EID: 49549094912     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2008.4484002     Document Type: Conference Paper

References (26)

1. A. H. Ajami, K. Banerjee, and M. Pedram. Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Transactions on CAD, 24(6):849-861, June 2005.
2. D. Atienza, P. D. Valle, G. Paci, F. Poletti, L. Benini, G. D. Micheli, and J. M. Mendias. A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip. In DAC, 2006.
3. J. Choi, C.-Y. Cher, H. Franke, H. Hamann, A. Weger, and P. Bose. Thermal-aware task scheduling at the system software level. In ISLPED, 2007.
4. A. K. Coskun, T. Rosing, and K. Whisnant. Temperature aware task scheduling in MPSoCs. In DATE, 2007.
5. M. Gomaa, M. D. Powell, and T. N. Vijaykumar. Heat-and-Run: leveraging SMT and CMP to manage power density through the operating system. In ASPLOS, 2004.
6. K. Gross, K. Whisnant, and A. Urmanov. Electronic prognostics through continuous system telemetry. In MFPT, pages 53-62, April 2006.
7. J. Hu and R. Marculescu. Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints. In DATE, 2004.
8. W.-L. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Thermal-aware task allocation and scheduling for embedded systems. In DATE, 2005.
9. Failure mechanisms and models for semiconductor devices, JEDEC publication JEP122C. http://www.jedec.org.
10. H. Kufluoglu and M. A. Alam. A computational model of NBTI and hot carrier injection time-exponents for MOSFET reliability. Journal of Computational Electronics, 3 (3):165-169, Oct. 2004.
11. E. Kursun, C.-Y. Cher, A. Buyuktosunoglu, and P.Bose. Investigating the effects of task scheduling on thermal behavior. In TACS, 2006.
12. C. J. Lasance. Thermally driven reliability issues in microelectronic systems: status-quo and challenges. Microelectronics Reliability, 43:1969-1974, 2003.
13. A. Leon, L. Jinuk, K. Tam, W. Bryg, F. Schumacher, P. Kongetira, D. Weisner, and A. Strong. A power-efficient high-throughput 32-thread SPARC processor. ISSCC, 2006.
14. J. Liu, P. H. Chou, N. Bagherzadeh, and F. Kurdahi. Power-aware scheduling under timing constraints for mission-critical embedded systems. In DAC, 2001.
15. Lp_solve. http://lpsolve.sourceforge.net/5.5/.
16. R. McDougall, J. Mauro, and B. Gregg. Solaris Performance and Tools. Sun Microsystems Press, 2006.
17. P. Rong and M. Pedram. Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system. In ASPDAC, 2006.
18. M. Ruggiero, A. Guerri, D. Bertozzi, F. Poletti, and M. Milano. Communication-aware allocation and scheduling framework for stream-oriented multi-processor system-on-chip. In DATE, 2006.
19. T. Simunic, K. Mihic, and G. D. Micheli. Optimization of reliability and power consumption in systems on a chip. In PATMOS, 2005.
20. K. Skadron, M. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. Temperature-aware microarchitecture. In ISCA, 2003.
21. SLAMD Distributed Load Engine. www.slamd.com.
22. J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers. The case for lifetime reliability-aware microprocessors. In ISCA, 2004.
23. H. Su, F. Liu, A. Devgan, E. Acar, and S. Nassif. Full-chip leakage estimation considering power supply and temperature variations. In ISLPED, 2003.
24. V. V. Vazirani. Approximation algorithms. Springer: Berlin, Germany, 2003.
25. R. Viswanath, V. Wakharkar, A. Watwe, and V. Lebonheur. Thermal performance challenges from silicon to systems. Intel Technology Journal, Q3, 2000.
26. Y. Zhang, X. S. Hu, and D. Z. Chen. Task scheduling and voltage selection for energy minimization. In DAC, 2002.