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Volumn , Issue , 2010, Pages

Wafer-to-wafer hybrid bonding technology for 3D IC

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; APPLICATION RANGE; BONDING ADHESIVE; BONDING PROPERTY; BONDING QUALITY; EUTECTIC BONDING; EVALUATION RESULTS; HYBRID BONDING; HYBRID SCHEME; MATERIAL CANDIDATE; METAL BONDING; MICRO GAPS; ON-WAFER; PAD SIZES; POLYMER MATERIALS; THERMO COMPRESSION BONDING; WAFER LEVEL; WHOLE PROCESS;

EID: 78651335467     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESTC.2010.5642848     Document Type: Conference Paper
Times cited : (20)

References (11)
  • 3
    • 34748922456 scopus 로고    scopus 로고
    • Simultaneous Cu - Cu and compliant dielectric bonding for 3D stacking of ICs
    • Jourdain A et al. Simultaneous Cu - Cu and compliant dielectric bonding for 3D stacking of ICs. In: Proceedings of IITC conference, June 4-6, 2007.
    • Proceedings of IITC Conference, June 4-6, 2007
    • Jourdain, A.1
  • 4
    • 64549139638 scopus 로고    scopus 로고
    • A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding
    • Liu F, Yu RR, Young AM, Doyle JP, Wang X, Shi L, et al. A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding. In: Proceedings of IEDM; 2008. p. 1-4.
    • Proceedings of IEDM; 2008 , pp. 1-4
    • Liu, F.1    Yu, R.R.2    Young, A.M.3    Doyle, J.P.4    Wang, X.5    Shi, L.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.