Superfine flip-chip interconnection in 20 μm-pitch utilizing reliable microthin underfill technology for 3D stacked LSI

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2002, Pages 1454-1459

  Umemoto, Mitsuo ^a   Tomita, Yoshihiro ^a   Morifuji, Tadahiro ^a   Ando, Tatsuya ^a   Sato, Tomotoshi ^a   Takahashi, Kenji ^a  

^a JAPAN AEROSPACE EXPLORATION AGENCY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

SUPERFINE FLIP-CHIP INTERCONNECTIONS;

ELECTROPLATING; FILLERS; FINITE ELEMENT METHOD; FLIP CHIP DEVICES; INTERCONNECTION NETWORKS; REACTIVE ION ETCHING; STRAIN; THERMAL EXPANSION;

LSI CIRCUITS;

EID: 0036282975     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2002.1008298     Document Type: Conference Paper

References (7)

1. Future system-on-silicon LSI chips
2. Current status of research and development for 3D chip stack technology
3. Flip-chip bonding technologies utilizing micro Au bumps in 20 μm-pitch
4. Micro bump interconnections and encapsulation technologies on 3D stacked LSI
5. Development of encapsulation for the plural narrow gaps of the three-dimensional stacked LSI
6. High-accuracy interconnection technologies on 3D stacking process
7. Structural design study of the 3D-stacked module with ultra-fine-pitch bumps