Development of wafer level underfill material and process

Proceedings of 5th Electronics Packaging Technology Conference, EPTC 2003

Volumn , Issue , 2003, Pages 194-198

  Zhang, Zhuqing ^a   Sun, Yangyang ^a   Fan, Lianhua ^a   Doraiswami, R ^b   Wong, C P ^a  

^a Georgia Institute of Technology   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CURING; ELECTRONICS PACKAGING; FLIP CHIP DEVICES;

AUTOCATALYTIC MODEL; HIGH CURING LATENCIES; INDIVIDUAL COMPONENTS; PRODUCTION EFFICIENCY; SOLDER JOINT RELIABILITY; STORAGE CAPABILITY; UNDERFILL MATERIALS; UNDERFILL TECHNOLOGY;

CHIP SCALE PACKAGES;

EID: 79960420293     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2003.1271515     Document Type: Conference Paper

References (7)

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