Thermal resistance measurements of interconnections, for the investigation of the thermal resistance of a three-dimensional (3D) chip stack

Annual IEEE Semiconductor Thermal Measurement and Management Symposium

Volumn , Issue , 2009, Pages 321-328

  Matsumoto, Keiji ^a   Taira, Yoichi ^a  

^a IBM RESEARCH TOKYO   (Japan)

Author keywords

Effective thermal conduction path; Interconnections; Thermal resistance; Three dimensional (3D) chip stack; Underfill

Indexed keywords

EFFECTIVE THERMAL CONDUCTION PATH; INTERCONNECTIONS; THERMAL RESISTANCE; THREE-DIMENSIONAL (3D) CHIP STACK; UNDERFILL;

COOLING; ELECTRIC RESISTANCE MEASUREMENT; INTEGRATED CIRCUITS; THERMAL CONDUCTIVITY; THERMAL VARIABLES MEASUREMENT; THERMOANALYSIS;

THREE DIMENSIONAL;

EID: 67649848108     PISSN: 10652221     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/STHERM.2009.4810783     Document Type: Conference Paper

References (18)

1. T. -Y. Chiang; S. J. Souri; C. O. Chui; K. C. Saraswat, "Thermal analysis of heterogeneous 3-D ICs with various integration scenarios ", International Electron Devices Meeting (IEDM), p.681, 2001.
2. M. Im; K. Banerjee, "Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs", International Electron Devices Meeting (IEDM), p.727, 2000.
3. K. Puttaswamy; G. H. Loh, "Thermal analysis of a 3D diestacked high-performance icroprocessors", Great Lakes Symposium on VLSI, p.19, 2006.
4. K. Puttaswamy; G. H. Loh, "Thermal herding: Microarchitecture techniques for controlling hotspots in high-performance 3Dintegrated processors", 13th IEEE International Symposium on High Performance Computer Architecture (HPCA), p.193, 2007.
5. S. Das; A. Chandrakasan; R. Reif, "Timing, energy and thermal performance of three-dimensional integrated circuits", Great Lakes Symposium on VLSI, p.338, 2004.
6. H. Hua; C. Mineo; K. Schoenfliess; A. Sule; A. Melamed; R. Jenkai; W. R. Davis, "Exploring compromises among timig, power and temperature in three-dimensional integrated circuits ", DAC, p.997, 2006.
7. T.-Y. Chiang; K. Banerjee; K. C. Saraswat, "Effect of via separation and low-k dielectric materials on the thermal characteristics of Cu Interconnects", International Electron Devices Meeting (IEDM)), p.261, 2000.
8. T.-Y. Chiang; K. Banerjee; K. C. Saraswat,. "Analytical thermal model for multilevel VLSI interconnects incorporating via effect", IEEE ELECTRON DEVICE LETTERS, vol.23, p.31, 2002.
9. T.-Y. Chiang; K. C. Saraswat, "Impact of vias on the thermal effect of deep sub-micron Cu/low-k interconnects", Symposium on VLSl Technology Digest of Technical Papers, p.141, 2001.
10. B. Goplen; S. Sapatnekar, "Thermal via placement in 3D ICs", ISPD, p.167, 2005.
11. H. Yu; Y. Shi; L. He; T. Karnik, "Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power", ISLPED, p.156, 2006.
12. Y. Yamaji; T. Ando; T. Morifuji; M. Tomisaka; M. Sunohara; T. Sato; K. Takahahi, "Thermal characterization of bare-die stacked module with Cu thorough-vias", Electronic Components and Technology Conferences, p.730, 2001.
13. J. N. Sweet; D. W. Peterson; D. Chu; B. L. Bainbridge; R. A. Gassman; C. A. Reber, "Analysis and measurement of thermal resistance in a 3-dimensional silicon multichip module populated with assembly test chips", 9th Annual IEEE Semiconductor Thermal Measurement and Management Symposium, p.1, 1993.
14. S. Gurrum; S. Suman; Y. Joshi; A. Fedorov; "Thermal issues in next-generation integrated circuits," IEEE Transactions on Device and Materials Reliability, vol. 4, p.709, 2004.
15. J.G. Bai; Z. Z Zhang.; G.-Q. Lu; D. P. H. Hasselman, "Measurement of solder/copper interfacial thermal resistance by the flash technique," Internatinal Journal of Thermophysics, vol.26, p.1607, 2005.
16. Y. Terada; K. Ohkubo; T. Mohri; T. Suzuki, "Thermal conductivity of intermetallic compounds with metallic bonds," Materials Transactions, vol.43, p.3167, 2002.
17. P. Jacobsson; B. Sundqvist, "Pressure dependence of the thermal and electrical conductivities of the intermetallic compounds AnCu ans AuCu3," J. Phys. Chem. Solids, vol.49, p.441, 1998.
18. K. Matsumoto; K. Sakuma; F. Yamada; Y. Taira, "Investigation of the thermal resistance of a three-dimensional (3D) chip stack from the thermal resistance measurement and modeling of a single-stacked-chip" , Internatinal Conference on Electronics Packaging, p.478, 2008.