Thermal analysis of hot spots in advanced 3D-stacked structures

15th International Workshop on Thermal Investigations of ICs and Systems, THERMINIC 2009

Volumn , Issue , 2009, Pages 56-60

  Torregiani, C ^a   Vandevelde, B ^a   Oprins, H ^a   Beyne, E ^a   De Wolf, I ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; ACTIVE LAYER; CIRCUIT OPERATION; DEVICE INTEGRATION; ELECTRICAL INTERCONNECTIONS; FINITE ELEMENT SIMULATIONS; HOT SPOT; MICROELECTRONIC CIRCUITS; SMALL PITCH; STACKED STRUCTURE; THERMAL ANALYSIS; THERMAL IMPACTS; THROUGH SILICON VIAS;

INTERCONNECTION NETWORKS; MICROELECTRONICS; STUDS (STRUCTURAL MEMBERS); THERMOANALYSIS; THREE DIMENSIONAL;

DIELECTRIC MATERIALS;

EID: 71749111930     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. st IEEE SEMI-THERM Symposium, pp. 307-312, March 2005.
2. S. Pinel et al, "Thermal modeling and management in ultrathin chip stack technology," IEEE Trans. On Components and Packaging Technologies, vol. 25, Issue 2, pp. 244-253, June 2002.
3. S. Im and K. Banerjee, "Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs," IEDM Tech. Dig., pp. 727-730, December 2000.
4. rd dimension for system integration," Proc. IEEE Int. Interconnect Technology Conference, pp. 1-5, 2006.
5. The International Technology Roadmap for Semiconductors (ITRS), ed. 2008. Available for free downloading, url: http://www.itrs.net/Links/2008ITRS/ Home2008.htm.
6. Msc. MARC, commercially available software, url: http://www.mscsoftware. com.
7. L. C. Chen, B. Vandevelde, B. Swinnen, E. Beyne, "Enabling SPICE-Type modeling of the thermal properties of 3D-stacked ICs," Electronics Packaging Technology Conference, pp. 492-499, December 2006.
8. V. Palankovski, S. Selberherr, "Thermal models for semiconductor device simulation," High Temperature Electronics, pp. 25-28, July 1999.
9. B. Swinnen et al, "3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias," Int. Electron Devices Meeting, pp. 1-4, December 2006.