Analytical and numerical modeling of the thermal performance of three-dimensional integrated circuits

IEEE Transactions on Components and Packaging Technologies

Volumn 33, Issue 1, 2010, Pages 56-63

  Jain, Ankur ^a   Jones, Robert E ^b   Chatterjee, Ritwik ^c   Pozder, Scott ^b  

^a MOLECULAR IMPRINTS INC   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Die stacking; Electrical thermal co design; Junction to air thermal resistance; Three dimensional (3D) integrated circuits (ICs); Through silicon via (TSV)

Indexed keywords

CO-DESIGNS; DIE STACKING; ELECTRICAL-THERMAL CO-DESIGN; THERMAL RESISTANCE; THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS; THROUGH-SILICON VIA (TSV);

DESIGN; DIES; ELECTRIC NETWORK ANALYSIS; ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; HEAT RESISTANCE; HEAT SINKS; INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS; INTERNET PROTOCOLS; MICROPROCESSOR CHIPS; MIXED CONVECTION; MODELS; PACKAGING; SILICON WAFERS; TEMPERATURE CONTROL; THERMODYNAMIC PROPERTIES;

THREE DIMENSIONAL;

EID: 77949567417     PISSN: 15213331     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAPT.2009.2020916     Document Type: Article

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