Thermal test vehicle for the validation of thermal modelling of hot spot dissipation in 3D stacked ICs

Electronics System Integration Technology Conference, ESTC 2010 - Proceedings

Volumn , Issue , 2010, Pages

  Oprins, H ^a   Cherman, V ^a   Torregiani, C ^a   Stucchi, M ^a   Vandevelde, B ^a   Beyne, E ^a  

^a IMEC   (Belgium)

Author keywords

3D stacked ICs; Experimental characterization; Thermal aware design; Thermal modelling

Indexed keywords

3D STACKED ICS; 3D STACKING; DIE PACKAGES; ELECTRONIC SYSTEMS; EXPERIMENTAL CHARACTERIZATION; EXPERIMENTAL SETUP; HIGHER TEMPERATURES; HOT SPOT; INTEGRATED HEATER; INTERCONNECTION STRUCTURE; PERFORMANCE ENHANCEMENTS; POWER DISSIPATION; STACKED DIE; STACKED DIE PACKAGES; STEADY STATE; TEMPERATURE PEAKS; TEST CHIPS; TEST VEHICLE; THERMAL BEHAVIOURS; THERMAL IMPACTS; THERMAL MODELLING; THERMAL SPREADING; THERMAL TESTS; THERMAL-AWARE DESIGN; THERMALLY CONDUCTIVE ADHESIVES; TRANSIENT TEMPERATURE;

AUTOMOBILE ELECTRONIC EQUIPMENT; DIES;

THREE DIMENSIONAL;

EID: 78651325862     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESTC.2010.5642955     Document Type: Conference Paper

References (15)

1. Beyne, E. "The Rise of the 3rd Dimension for System Integration", Proc. IEEE IITC, pp. 1-5, 2006.
2. JEDEC Standard, JEP-158 3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Evaluating and Understanding Reliability Interactions, www.jedec.org
3. Sapatnekar, S.S. "Addressing thermal and power delivery bottlenecks in 3D circuits", 2009.
4. Cong, J.; Wei, ,J.; Zhang, Y., "A thermal-driven floorplanning algorithm for 3D ICs," ICCAD 2004, pp.306-313
5. Oprins, H.; Cupak, M.; Van Der Plas, G.; Vandevelde, B.; Srinivasan, A.; Cheng, E.;"Fine Grain Thermal Modelling of 3D Stacked Structures", THERMINIC 2009.
6. HeatWave-3DIC (Nanoscale Full-Chip Thermal Simulator), Gradient Design Automation, Inc, http://www.gradient-da.com/
7. Turowski, M.; Dooley, S.; Raman, A.; Casto, M.; "Multiscale 3D thermal analysis of analog ICs: From full-chip to device level", 14th International Workshop on Thermal Inveatigation of ICs and Systems, pp. 64-69, 2008.
8. Rencz, M.; Székely V.; "Structure function evaluation of stacked dies", Proceedings of the XXth SEMI-THERM Symposium, March 9-11, San Jose, CA, USA, pp 50-55, 2004.
9. Enrico A. Garcia, Chia-Pin Chiu, "Compact Modelling Approaches to Multiple Die Stacked Chip Scale Packages"., 19th IEEE SEMI-THERM Symposium, pp. 160-167, 2003.
10. Zhang, L.; Howard, N.; Gumaste, V.; Poddar, A.; Nguyen, L.; "Thermal Characterization of Stacked-Die Packages", 20th IEEE SEMI-THERM Symposium, pp. 55-63, 2004.
11. Oprins H. et al., "Fine grain thermal modeling and experimental validation of 3D-ICs", Accepted for publication in Microelectronics Journal, May 2010.
12. Swinnen, B.; Ruythooren, W.; De Moor, P.; Bogaerts, L.; Carbonell, L.; De Munck, K.; Eyckens, B.; Stoukatch, S.; Sabuncuoglu Tezcan, D.; Tokei, Z.; Vaes, J.; Van Aelst, J. and Beyne, E.; "3D integration by Cu-Cu thermocompression bonding of extremely thinned bulk Si die containing 10μm pitch through Si vias", Proc. IEDM Conference, December 11-13,2006, San Fransisco.
13. Swinnen, B.; Jourdain, A.; De Moor, P.; Beyne E.; Chapter in Wafer Level 3-D ICs Process Technology; edited by S. Tan, R.J. Gutmann, and L.R. Reif (Eds), Springer, ISBN 978-0-387-76532-7, 2008.
14. Torregiani, C.; Oprins, H.; Vandevelde, B.; Beyne, E.; De Wolf, I.;" Compact thermal modeling of hot spots in advanced 3D-stacked structures", Proc. EPTC 2009, pp. 131-136.
15. Torregiani, C.; Oprins, H.; Vandevelde, B.; Beyne, E.; De Wolf, I.; "Thermal analysis of hot spots in advanced 3D-stacked structures", THERMINIC 2009.