Compact thermal modeling of hot spots in advanced 3D-stacked ICs

Proceedings of the Electronic Packaging Technology Conference, EPTC

Volumn , Issue , 2009, Pages 131-136

  Torregiani, C ^a   Oprins, H ^a   Vandevelde, B ^a   Beyne, E ^a   De Wolf, I ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COMPACT THERMAL MODELING; COMPACT THERMAL MODELS; DIE STACK; GRAPHICAL INTERFACE; GRID SIZE; HOT SPOT; NON-UNIFORM HEAT SOURCE; PACKAGE RESISTANCE; PARAMETERIZED; PREDICTION TOOLS; STACKED DIE; STRUCTURAL PARAMETER; STRUCTURE GEOMETRY; THERMAL DISTRIBUTIONS; THERMAL MANAGEMENT; THERMAL PROPERTIES; USER FRIENDLY;

CHIP SCALE PACKAGES; DIES; MATERIALS PROPERTIES; STRUCTURAL OPTIMIZATION; THERMOANALYSIS; THERMODYNAMIC PROPERTIES;

THREE DIMENSIONAL;

EID: 77950958016     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2009.5416563     Document Type: Conference Paper

References (12)

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