Efficient thermal aware placement approach integrated with 3D DCT placement algorithm

Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Volumn , Issue , 2008, Pages 289-292

  Yan, Haixia ^a   Zhou, Qiang ^a   Hong, Xianlong ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE DISTRIBUTION; CLUTCHES; COSINE TRANSFORMS; DISCRETE COSINE TRANSFORMS; ELECTRONICS ENGINEERING; MATHEMATICAL TRANSFORMATIONS; QUADRATIC PROGRAMMING; THERMOANALYSIS; WIRE;

3-D ICS; AVERAGE TEMPERATURES; CELL DISTRIBUTIONS; ELECTRONIC DESIGNS; FAST METHODS; INTERCONNECT DELAYS; INTERNATIONAL SYMPOSIUM; PLACEMENT ALGORITHMS; PLACEMENT APPROACH; QUADRATIC FUNCTIONS; QUADRATIC PLACEMENT; WIRE LENGTHS;

ITERATIVE METHODS;

EID: 49749142049     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2008.4479741     Document Type: Conference Paper

References (11)

1. W. K. Chu and W. H. Kao ,"A three-dimensional transient electro thermal simulation system for IC's", Proc 1stTHERMINIC Workshop, pp201-207 Sept. 1995.
2. Y. K. Tsui, S. W. R. Lee, J. S. Wu, J. K. Kim and M. M. F.Yuen, "Three-dimensional packaging for multi-chip modulewiththrough-the-silicon via hole", Electronics PackagingTechnology, 5th Conference, pp 1-7 2003.
3. C. H. Tsai and S. M. Kang, "Cell-Level Placement for Improving Substrate Thermal Distribution", IEEE Trans On Compute.-Aided Design, vol. 19, no. 2, pp. 253-266, Feb 2000.
4. B. Goplen and S. S. Sapatnekar, "Efficient thermal placement of standard cells in 3D ICs using a force Directed approach", Proc. Int. Conf. on Computer-Aided Design, pp. 86-89, 2003.
5. Carsten Recke and Alfred Eder, "Timing - and Thermal -Oriented Placement for Multi-Chip Modules", ASIC Conference and Exhibit, pp. 555-558, 1993.
6. H.Yan, Z.Li, X.Hong and Q.Zhou, "Unified quadratic programming approach for 3-D mixed mode placement", in Proc. ISCAS, pp 3411-3414, 2007.
7. Cong Jason, Luo Guojie, Wei Jie and Zhang, Yan, "Thermal-aware 3D IC Placement Via Transformation", Proc of ASP-DAC, pp.780-785, 2007.
8. P.Wilkerson, A. Raman, M. Turowski, "Fast, Automated Thermal Simulation of Three-Dimensional Integrated Circuits", ITherm 2004, Nevada, 1-4 June 2004.
9. P. Wilkerson, M. Furmanczyk and M. Turowski, "Compact thermal modeling analysis for 3D integration circuits", in Proc. Int. Conf. Mixed Design of Integrated Circuits and Systems, 2004, pp.24-26.
10. Cong. J, Jie Wei and Yan Zhang, "A thermal-driven floorplanning algorithm for 3D ICs", Proc. Int. Conf. on Computer-Aided Design, pp. 306 - 313, 2004.
11. http://www.public.iastate.edu/∼nataraj/ISPD04_Bench.html.