메뉴 건너뛰기




Volumn 46, Issue 1, 2011, Pages 293-307

Design issues and considerations for low-cost 3-D TSV IC technology

(37)  Van Der Plas, Geert a   Limaye, Paresh a   Loi, Igor g   Mercha, Abdelkarim a   Oprins, Herman a   Torregiani, Cristina c   Thijs, Steven a   Linten, Dimitri a   Stucchi, Michele a   Katti, Guruprasad a,b   Velenis, Dimitrios a   Cherman, Vladimir a   Vandevelde, Bart a   Simons, Veerle a   De Wolf, Ingrid a   Labie, Riet a   Perry, Dan c   Bronckers, Stephane d   Minas, Nikolaos a   Cupac, Miro a   more..

a IMEC   (Belgium)

Author keywords

3 D; CU TSV; ESD; mechanical stress; network on chip; noise coupling; thermal behavior

Indexed keywords

3-D; CU TSV; ESD; MECHANICAL STRESS; NETWORK ON CHIP; NOISE COUPLING; THERMAL BEHAVIORS;

EID: 78650861793     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2074070     Document Type: Conference Paper
Times cited : (223)

References (28)
  • 1
    • 79961208982 scopus 로고    scopus 로고
    • Stackable memory of 3-D chip integration for mobile applications
    • S. Gu et al., "Stackable memory of 3-D chip integration for mobile applications," in Proc. IEDM '08, pp. 1-4.
    • Proc. IEDM '08 , pp. 1-4
    • Gu, S.1
  • 2
    • 70349300546 scopus 로고    scopus 로고
    • 8 Gb 3-D DDR3 DRAM using through-silicon-via technology
    • 07.2
    • U. Kang et al., "8 Gb 3-D DDR3 DRAM using through-silicon-via technology," in Proc. ISSCC 09, pp. 130-131, 07.2.
    • Proc. ISSCC 09 , pp. 130-131
    • Kang, U.1
  • 3
    • 70349295866 scopus 로고    scopus 로고
    • Chip-scale camera module (CSCM) using through-silicon-via (TSV)
    • 28.5
    • H. Yoshikawa et al., "Chip-scale camera module (CSCM) using through-silicon-via (TSV)," in Proc. ISSCC 09, pp. 476-477, 28.5.
    • Proc. ISSCC 09 , pp. 476-477
    • Yoshikawa, H.1
  • 4
    • 78650919804 scopus 로고    scopus 로고
    • A 4-side tileable back-illuminated 3-D-integrated mpixel CMOS image sensor
    • 02.1
    • Y. Suntharalingam et al., "A 4-side tileable back-illuminated 3-D-integrated mpixel CMOS image sensor," in Proc. ISSCC 09, 02.1.
    • Proc. ISSCC 09
    • Suntharalingam, Y.1
  • 5
    • 78650905676 scopus 로고    scopus 로고
    • A 1.8 v 30 nJ adaptive program-voltage (20 V) generator for 3-D-integrated NAND flash SSD
    • 13.5
    • K. Ishida et al., "A 1.8 V 30 nJ adaptive program-voltage (20 V) generator for 3-D-integrated NAND flash SSD," in Proc. ISSCC 09, pp. 38-39, 13.5.
    • Proc. ISSCC 09 , pp. 38-39
    • Ishida, K.1
  • 6
    • 71449116253 scopus 로고    scopus 로고
    • 3-D stacked IC demonstration using a through silicon via first approach
    • J. Van Olmen et al., "3-D stacked IC demonstration using a through silicon via first approach," in Proc. IEDM, 2008, pp. 303-306.
    • (2008) Proc. IEDM , pp. 303-306
    • Van Olmen, J.1
  • 7
    • 33750592887 scopus 로고    scopus 로고
    • Three-dimensional integration technology based on wafer bonding with vertical buried interconnections
    • Nov.
    • M. Koyanagi, T. Nakamura, Y. Yamada, H. Kikuchi, T. Fukushima, T. Tanaka, and H. Kurino, "Three-dimensional integration technology based on wafer bonding with vertical buried interconnections," IEEE Trans. Electron Devices, vol. 53, no. 11, pp. 2799-2808, Nov. 2006.
    • (2006) IEEE Trans. Electron Devices , vol.53 , Issue.11 , pp. 2799-2808
    • Koyanagi, M.1    Nakamura, T.2    Yamada, Y.3    Kikuchi, H.4    Fukushima, T.5    Tanaka, T.6    Kurino, H.7
  • 9
    • 70549109040 scopus 로고    scopus 로고
    • Through-silicon via and die stacking technologies for microsystems-integration
    • E. Beyne et al., "Through-silicon via and die stacking technologies for microsystems-integration," in Proc. IEDM, 2008, pp. 1-4.
    • (2008) Proc. IEDM , pp. 1-4
    • Beyne, E.1
  • 12
    • 85086952678 scopus 로고    scopus 로고
    • Three-dimensional integrated circuits for lowpower, highbandwidth systems on a chip
    • R. Chatterjeea et al., "Three-dimensional integrated circuits for lowpower, highbandwidth systems on a chip," in Proc. IEEE Int. Interconnect Technol. Conf., 2007, pp. 81-83.
    • (2007) Proc. IEEE Int. Interconnect Technol. Conf. , pp. 81-83
    • Chatterjeea, R.1
  • 14
    • 78650879549 scopus 로고    scopus 로고
    • Development of 3-D-packaging process technology for stacked memory chips
    • MA Nov. 27-29
    • T. Mitsuhashi et al., "Development of 3-D-packaging process technology for stacked memory chips," in Proc. Enabling Technologies for 3-D Integration Symp., Boston, MA, Nov. 27-29, 2006, pp. 155-62.
    • (2006) Proc. Enabling Technologies for 3-D Integration Symp., Boston , pp. 155-62
    • Mitsuhashi, T.1
  • 15
    • 63049135179 scopus 로고    scopus 로고
    • Through silicon vias technology for CMOS image sensors packaging: Presentation of technology and electrical results
    • Singapore Dec. 9-12
    • D. Henry et al., "Through silicon vias technology for CMOS image sensors packaging: Presentation of technology and electrical results," in Proc. EPTC 2008, Singapore, Dec. 9-12, 2008, pp. 35-44.
    • (2008) Proc. EPTC 2008 , pp. 35-44
    • Henry, D.1
  • 16
    • 77952233876 scopus 로고    scopus 로고
    • Design issues and solutions for low-cost 3-D TSV IC technology
    • 07.8
    • G. Van der Plas et al., "Design issues and solutions for low-cost 3-D TSV IC technology," in Proc. ISSCC 10, pp. 148-149, 07.8.
    • Proc. ISSCC 10 , pp. 148-149
    • Plas Der G.Van1
  • 17
    • 70349668537 scopus 로고    scopus 로고
    • Electrically yielding collective hybrid bonding for 3-D stacking of ICs
    • A. Jourdain et al., "Electrically yielding collective hybrid bonding for 3-D stacking of ICs," in Proc. ECTC, 2009, pp. 11-13.
    • (2009) Proc. ECTC , pp. 11-13
    • Jourdain, A.1
  • 18
    • 73349133689 scopus 로고    scopus 로고
    • Electrical modeling and characterization of through silicon via for three-dimensional ICs
    • Jan.
    • G. Katti et al., "Electrical modeling and characterization of through silicon via for three-dimensional ICs," IEEE Trans. Electron Devices, vol. 57, no. 1, pp. 256-262, Jan. 2010.
    • (2010) IEEE Trans. Electron Devices , vol.57 , Issue.1 , pp. 256-262
    • Katti, G.1
  • 19
    • 50949109688 scopus 로고    scopus 로고
    • Extraction of the appropriate material property for realistic modeling of through-silicon-vias using μ-Raman spectroscopy
    • C. Okoro et al., "Extraction of the appropriate material property for realistic modeling of through-silicon-vias using μ-Raman spectroscopy," in Proc. IITC 08, pp. 16-18.
    • Proc. IITC 08 , pp. 16-18
    • Okoro, C.1
  • 20
    • 78651545525 scopus 로고    scopus 로고
    • Design for manufacturability for fabless manufacturers
    • Mar.
    • R. Radojcic et al., "Design for manufacturability for fabless manufacturers," IEEE Solid-State Circuits Mag., vol. 1, no. 3, pp. 25-33, Mar. 2009.
    • (2009) IEEE Solid-State Circuits Mag , vol.1 , Issue.3 , pp. 25-33
    • Radojcic, R.1
  • 21
    • 71749118577 scopus 로고    scopus 로고
    • Fine grain thermal modeling of 3-D stacked structures
    • H. Oprins et al., "Fine grain thermal modeling of 3-D stacked structures," in Proc. THERMINIC, 2009, pp. 45-49.
    • (2009) Proc. THERMINIC , pp. 45-49
    • Oprins, H.1
  • 22
    • 71749111930 scopus 로고    scopus 로고
    • Thermal analysis of hot spots in advanced 3-Dstacked structures
    • C. Torregiani et al., "Thermal analysis of hot spots in advanced 3-Dstacked structures," in Proc. THERMINIC, 2009, pp. 56-60.
    • (2009) Proc. THERMINIC , pp. 56-60
    • Torregiani, C.1
  • 23
    • 78650886694 scopus 로고    scopus 로고
    • Fine grain thermal modeling and experimental validation of 3-D-ICs
    • Nov. submitted for publication
    • H. Oprins et al., "Fine grain thermal modeling and experimental validation of 3-D-ICs," Microelectronics J., Nov. 2009, submitted for publication.
    • (2009) Microelectronics J.
    • Oprins, H.1
  • 24
    • 78650904724 scopus 로고    scopus 로고
    • A wafer-scale 3-D circuit integration technology
    • C. Torregiani et al., "A wafer-scale 3-D circuit integration technology," in Proc. EPTC, 2009, pp. 131-136.
    • (2009) Proc. EPTC , pp. 131-136
    • Torregiani, C.1
  • 25
    • 22544484814 scopus 로고    scopus 로고
    • Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates
    • Jul.
    • C. Soens, G.Van der Plas, P.Wambacq, S. Donnay, and M.Kuijk, "Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates," IEEE J. Solid-State Electron., vol. 40, no. 7, pp. 1472-1481, Jul. 2005.
    • (2005) IEEE J. Solid-State Electron. , vol.40 , Issue.7 , pp. 1472-1481
    • Soens, C.1    Van Der Plas, G.2    Wambacq, P.3    Donnay, S.4    Kuijk, M.5
  • 26
    • 34548858682 scopus 로고    scopus 로고
    • An 80-Tile 1.28 TFLOPS network-on-chip in 65 nm CMOS
    • S. Vangal et al., "An 80-Tile 1.28 TFLOPS network-on-chip in 65 nm CMOS," in Proc. ISSCC, 2007, pp. 98-99.
    • (2007) Proc. ISSCC , pp. 98-99
    • Vangal, S.1
  • 27
    • 49549105341 scopus 로고    scopus 로고
    • A 125 GOPS 583 mW network-on-chip based parallel processor with bio-inspired visual attention engine
    • K. Kim et al., "A 125 GOPS 583 mW network-on-chip based parallel processor with bio-inspired visual attention engine," in Proc. ISSCC 08, p. 308.
    • Proc. ISSCC 08 , pp. 308
    • Kim, K.1
  • 28
    • 57849122475 scopus 로고    scopus 로고
    • A low-overhead fault tolerance scheme for TSV-based 3-D network on chip links
    • I. Loi et al., "A low-overhead fault tolerance scheme for TSV-based 3-D network on chip links," in Proc. ICCAD 08, pp. 598-602.
    • Proc. ICCAD 08 , pp. 598-602
    • Loi, I.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.