From defects creation to circuit reliability - A bottom-up approach (invited)

Microelectronic Engineering

Volumn 88, Issue 7, 2011, Pages 1396-1407

  Huard, V ^a   Cacho, F ^a   Mamy Randriamihaja, Y ^a,b   Bravaix, A ^b  

^a STMICROELECTRONICS   (France)

^b Institut Superieur de l'Electronique et du Numerique   (France)

Author keywords

Bias temperature stress; Border traps; Channel cold carriers; Design in Reliability; Device lifetime; Hot Carrier degradation; Interface traps generation; Multi vibrational excitation; Spice models; Trapped oxide charges; Ultra thin gate oxide

Indexed keywords

BIAS TEMPERATURE STRESS; BORDER TRAPS; COLD CARRIERS; DESIGN-IN RELIABILITY; DEVICE LIFETIME; HOT-CARRIER DEGRADATION; INTERFACE TRAPS GENERATION; MULTI-VIBRATIONAL EXCITATION; SPICE MODELS; TRAPPED OXIDE CHARGES; ULTRA-THIN;

DESIGN; MODELS; RELIABILITY; SPICE;

INTEGRATED CIRCUITS;

EID: 79958046345     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2011.03.101     Document Type: Conference Paper

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