Designing in reliability in advanced CMOS technologies

Microelectronics Reliability

Volumn 46, Issue 9-11, 2006, Pages 1464-1471

  Parthasarathy, C R ^a,c   Denais, M ^a   Huard, V ^b   Ribes, G ^a   Roy, D ^a   Guerin, C ^a   Perrier, F ^b   Vincent, E ^a   Bravaix, A ^c  

^a STMICROELECTRONICS   (France)

^b NXP SEMICONDUCTORS   (Netherlands)

^c AIX MARSEILLE UNIVERSITÉ   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; NIOBIUM COMPOUNDS; OPTIMIZATION; RELIABILITY;

BIAS PATTERNS; DESIGN-IN RELIABILITY METHODOLOGY; ON-THE-FLY (OTF) METHODOLOGY;

CMOS INTEGRATED CIRCUITS;

EID: 33748129950     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2006.07.012     Document Type: Article

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