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Volumn , Issue , 2011, Pages 423-430

A stacked mesh 3D NOC architecture enabling congestion-aware and reliable inter-layer communication

Author keywords

3D ICs; 3D NoC Bus Hybrid Architecture; Fault Tolerance; Routing Algorithm

Indexed keywords

3-D ICS; 3D NOC-BUS HYBRID ARCHITECTURE; BUFFER UTILIZATION; CONGESTION-AWARE; EFFICIENT ARCHITECTURE; HOT SPOT; INTER-LAYER COMMUNICATION; INTERMEDIATE BUFFERS; LOAD-BALANCING; NEGATIVE EXPONENTIAL DISTRIBUTION; NOC ARCHITECTURES; PERFORMANCE IMPROVEMENTS; POWER CONSUMPTION; PROPOSED ARCHITECTURES; REAL APPLICATIONS; SYSTEM ANALYSIS; SYSTEM FAULTS; TRAFFIC PATTERN; VIDEO CONFERENCE; WIRING DELAY;

EID: 79955028003     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PDP.2011.39     Document Type: Conference Paper
Times cited : (14)

References (22)
  • 1
    • 33846118079 scopus 로고    scopus 로고
    • Designing reliable systems from unreliable components: The challenges of transistor variability and degradation
    • DOI 10.1109/MM.2005.110
    • S. Borkar, "Designing reliable systems from unreliable components: The challenges of transistor variability and degradation," IEEE Micro, Vol. 25, No. 6, 2005, pp. 10-16. (Pubitemid 46567817)
    • (2005) IEEE Micro , vol.25 , Issue.6 , pp. 10-16
    • Borkar, S.1
  • 4
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new SoC paradigm
    • DOI 10.1109/2.976921
    • L. Benini and G. D. Micheli, "Networks on chips: A new SoC paradigm," IEEE Computer, Vol. 35, No. 1, 2002, pp. 70-78. (Pubitemid 34069383)
    • (2002) Computer , vol.35 , Issue.1 , pp. 70-78
    • Benini, L.1    De Micheli, G.2
  • 5
    • 33745800231 scopus 로고    scopus 로고
    • A survey of research and practices of network-on-chip
    • T. Bjerregaard, and S. Mahadevan, "A Survey of Research and Practices of Network-on-Chip", ACM Computing Surveys, Vol. 38, No. 1, 2006, pp. 1-51.
    • (2006) ACM Computing Surveys , vol.38 , Issue.1 , pp. 1-51
    • Bjerregaard, T.1    Mahadevan, S.2
  • 8
    • 57349168074 scopus 로고    scopus 로고
    • Networks-on-chip in a three-dimensional environment: A performance evaluation
    • B. S. Feero and P. P. Pande, "Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation," IEEE Transactions on Computers, Vol. 58, No. 1, 2009, pp. 32-45.
    • (2009) IEEE Transactions on Computers , vol.58 , Issue.1 , pp. 32-45
    • Feero, B.S.1    Pande, P.P.2
  • 9
    • 77957928299 scopus 로고    scopus 로고
    • An efficient 3D NoC architecture using bidirectional bisynchronous vertical channels
    • A.-M. Rahmani et al., "An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels," in Proc. of IEEE Computer Society Annual Symposium on VLSI, 2010, pp. 452-453.
    • (2010) Proc. of IEEE Computer Society Annual Symposium on VLSI , pp. 452-453
    • Rahmani, A.-M.1
  • 10
    • 33947407658 scopus 로고    scopus 로고
    • Three-dimensional integrated circuits and the future of system-on-chip designs
    • DOI 10.1109/JPROC.2006.873612
    • R. S. Patti, "Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs", in Proc of IEEE, Vol. 94, No. 6, 2006, pp. 1214-1224. (Pubitemid 46444967)
    • (2006) Proceedings of the IEEE , vol.94 , Issue.6 , pp. 1214-1224
    • Patti, R.S.1
  • 11
    • 70349811603 scopus 로고    scopus 로고
    • Networks-on-chip in emerging interconnect paradigms: Advantages and challenges
    • L. P. Carloni et al., "Networks-on-Chip in Emerging Interconnect Paradigms: Advantages and Challenges," in Proc. of International Symposium on Networks-on-Chip, 2009, pp. 93-109.
    • (2009) Proc. of International Symposium on Networks-on-chip , pp. 93-109
    • Carloni, L.P.1
  • 14
    • 77955691383 scopus 로고    scopus 로고
    • A layer-multiplexed 3D on-chip network architecture
    • R. S. Ramanujam and B. Lin, "A Layer-Multiplexed 3D On-Chip Network Architecture," IEEE Embedded Systems Letters, Vol. 1, No. 2, 2009, pp. 50-55.
    • (2009) IEEE Embedded Systems Letters , vol.1 , Issue.2 , pp. 50-55
    • Ramanujam, R.S.1    Lin, B.2
  • 17
  • 18
    • 77955711245 scopus 로고    scopus 로고
    • EDXY - A low cost congestion-aware routing algorithm for network-on-chips
    • P. Lotfi-Kamran et al., "EDXY - A low cost congestion-aware routing algorithm for network-on-chips," Journal of Systems Architecture, Vol. 56, No. 7, 2010, pp. 256-264.
    • (2010) Journal of Systems Architecture , vol.56 , Issue.7 , pp. 256-264
    • Lotfi-Kamran, P.1
  • 21
    • 72749091105 scopus 로고    scopus 로고
    • NED: A novel synthetic traffic pattern for power/performance analysis of network-on-chips using negative exponential distribution
    • A.-M. Rahmani et al., "NED: A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-chips Using Negative Exponential Distribution," Journal of Low Power Electronics, Vol. 5, No. 3, 2009, pp. 396-405.
    • (2009) Journal of Low Power Electronics , vol.5 , Issue.3 , pp. 396-405
    • Rahmani, A.-M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.