-
1
-
-
33846118079
-
Designing reliable systems from unreliable components: The challenges of transistor variability and degradation
-
DOI 10.1109/MM.2005.110
-
S. Borkar, "Designing reliable systems from unreliable components: The challenges of transistor variability and degradation," IEEE Micro, Vol. 25, No. 6, 2005, pp. 10-16. (Pubitemid 46567817)
-
(2005)
IEEE Micro
, vol.25
, Issue.6
, pp. 10-16
-
-
Borkar, S.1
-
4
-
-
0036149420
-
Networks on chips: A new SoC paradigm
-
DOI 10.1109/2.976921
-
L. Benini and G. D. Micheli, "Networks on chips: A new SoC paradigm," IEEE Computer, Vol. 35, No. 1, 2002, pp. 70-78. (Pubitemid 34069383)
-
(2002)
Computer
, vol.35
, Issue.1
, pp. 70-78
-
-
Benini, L.1
De Micheli, G.2
-
5
-
-
33745800231
-
A survey of research and practices of network-on-chip
-
T. Bjerregaard, and S. Mahadevan, "A Survey of Research and Practices of Network-on-Chip", ACM Computing Surveys, Vol. 38, No. 1, 2006, pp. 1-51.
-
(2006)
ACM Computing Surveys
, vol.38
, Issue.1
, pp. 1-51
-
-
Bjerregaard, T.1
Mahadevan, S.2
-
6
-
-
33748533457
-
Three-dimensional integrated circuits
-
DOI 10.1147/rd.504.0491
-
A. W. Topol et al., "Three-Dimensional Integrated Circuits," IBM J. Research and Development, Vol. 50, No. 4/5, July-Sept. 2006, pp. 491-506. (Pubitemid 44364166)
-
(2006)
IBM Journal of Research and Development
, vol.50
, Issue.4-5
, pp. 491-506
-
-
Topol, A.W.1
La Tulipe Jr., D.C.2
Shi, L.3
Frank, D.J.4
Bernstein, K.5
Steen, S.E.6
Kumar, A.7
Singco, G.U.8
Young, A.M.9
Guarini, K.W.10
Ieong, M.11
-
7
-
-
34648854453
-
3-D topologies for networks-on-chip
-
DOI 10.1109/TVLSI.2007.893649
-
V. F. Pavlidis and E. G. Friedman, "3-D Topologies for Networks-on-Chip," in Proc. of IEEE Trans. Of VLSI Systems., Vol. 15, No. 10, 2007, pp.1081-1090. (Pubitemid 47460369)
-
(2007)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.15
, Issue.10
, pp. 1081-1090
-
-
Pavlidis, V.F.1
Friedman, E.G.2
-
8
-
-
57349168074
-
Networks-on-chip in a three-dimensional environment: A performance evaluation
-
B. S. Feero and P. P. Pande, "Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation," IEEE Transactions on Computers, Vol. 58, No. 1, 2009, pp. 32-45.
-
(2009)
IEEE Transactions on Computers
, vol.58
, Issue.1
, pp. 32-45
-
-
Feero, B.S.1
Pande, P.P.2
-
9
-
-
77957928299
-
An efficient 3D NoC architecture using bidirectional bisynchronous vertical channels
-
A.-M. Rahmani et al., "An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels," in Proc. of IEEE Computer Society Annual Symposium on VLSI, 2010, pp. 452-453.
-
(2010)
Proc. of IEEE Computer Society Annual Symposium on VLSI
, pp. 452-453
-
-
Rahmani, A.-M.1
-
10
-
-
33947407658
-
Three-dimensional integrated circuits and the future of system-on-chip designs
-
DOI 10.1109/JPROC.2006.873612
-
R. S. Patti, "Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs", in Proc of IEEE, Vol. 94, No. 6, 2006, pp. 1214-1224. (Pubitemid 46444967)
-
(2006)
Proceedings of the IEEE
, vol.94
, Issue.6
, pp. 1214-1224
-
-
Patti, R.S.1
-
11
-
-
70349811603
-
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges
-
L. P. Carloni et al., "Networks-on-Chip in Emerging Interconnect Paradigms: Advantages and Challenges," in Proc. of International Symposium on Networks-on-Chip, 2009, pp. 93-109.
-
(2009)
Proc. of International Symposium on Networks-on-chip
, pp. 93-109
-
-
Carloni, L.P.1
-
12
-
-
35348908288
-
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
-
DOI 10.1145/1250662.1250680, ISCA'07: 34th Annual International Symposium on Computer Architecture, Conference Proceedings
-
J. Kim et al., "A novel dimensionaly-decomposed router for on-chip communication in 3D architectures," in Proc. of International Symposium on Computer Architectures, 2007. pp. 138-149. (Pubitemid 47582098)
-
(2007)
Proceedings - International Symposium on Computer Architecture
, pp. 138-149
-
-
Kim, J.1
Nicopoulos, C.2
Park, D.3
Das, R.4
Xie, Y.5
Narayanan, V.6
Yousif, M.S.7
Das, C.R.8
-
13
-
-
33845914023
-
Design and management of 3D chip multiprocessors using network-in-memory
-
DOI 10.1109/ISCA.2006.18, 1635947, Proceedings - 33rd International Symposium on Computer Architecture,ISCA 2006
-
F. Li et al., "Design and Management of 3D Chip Multiprocessors Using Network-in-Memory," in Proc. of International Symposium on Computer Architecture, 2006, pp. 130-141. (Pubitemid 46016610)
-
(2006)
Proceedings - International Symposium on Computer Architecture
, vol.2006
, pp. 130-141
-
-
Li, F.1
Nicopoulos, C.2
Richardson, T.3
Xie, Y.4
Narayanan, V.5
Kandemir, M.6
-
14
-
-
77955691383
-
A layer-multiplexed 3D on-chip network architecture
-
R. S. Ramanujam and B. Lin, "A Layer-Multiplexed 3D On-Chip Network Architecture," IEEE Embedded Systems Letters, Vol. 1, No. 2, 2009, pp. 50-55.
-
(2009)
IEEE Embedded Systems Letters
, vol.1
, Issue.2
, pp. 50-55
-
-
Ramanujam, R.S.1
Lin, B.2
-
15
-
-
0017441638
-
A large scale, homogeneous, fully distributed parallel machine
-
H. Sullivan and T. R. Bashkow, "A large scale, homogeneous, fully distributed parallel machine," in Proc. of International Symposium on Computer Architecture, 1977, pp. 105-117.
-
(1977)
Proc. of International Symposium on Computer Architecture
, pp. 105-117
-
-
Sullivan, H.1
Bashkow, T.R.2
-
18
-
-
77955711245
-
EDXY - A low cost congestion-aware routing algorithm for network-on-chips
-
P. Lotfi-Kamran et al., "EDXY - A low cost congestion-aware routing algorithm for network-on-chips," Journal of Systems Architecture, Vol. 56, No. 7, 2010, pp. 256-264.
-
(2010)
Journal of Systems Architecture
, vol.56
, Issue.7
, pp. 256-264
-
-
Lotfi-Kamran, P.1
-
19
-
-
77953096507
-
TSV redundancy: Architecture and design issues in 3D IC
-
A.-C. Hsieh et al., "TSV Redundancy: Architecture and Design Issues in 3D IC," in Proc. of International Conference on Design, Automation, and Test in Eroupe, 2010, pp. 166-171.
-
(2010)
Proc. of International Conference on Design, Automation, and Test in Eroupe
, pp. 166-171
-
-
Hsieh, A.-C.1
-
21
-
-
72749091105
-
NED: A novel synthetic traffic pattern for power/performance analysis of network-on-chips using negative exponential distribution
-
A.-M. Rahmani et al., "NED: A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-chips Using Negative Exponential Distribution," Journal of Low Power Electronics, Vol. 5, No. 3, 2009, pp. 396-405.
-
(2009)
Journal of Low Power Electronics
, vol.5
, Issue.3
, pp. 396-405
-
-
Rahmani, A.-M.1
|