A layer-multiplexed 3D on-chip network architecture

IEEE Embedded Systems Letters

Volumn 1, Issue 2, 2009, Pages 50-55

  Sunkam Ramanujam, Rohit ^a   Lin, Bill ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

3D; 3D mesh; Integrated circuits (ICs); Oblivious routing

Indexed keywords

3D; 3D MESHES; 3D NETWORKS; 3D TECHNOLOGY; AVERAGE THROUGHPUT; DESIGN OPTION; EMBEDDED APPLICATION; HOP COUNT; LOAD-BALANCED; MANY-CORE; MESH ARCHITECTURE; OBLIVIOUS ROUTING; ON-CHIP NETWORKS; POWER EFFICIENT; WIRING DELAY; WORST-CASE THROUGHPUT;

COMPUTER ARCHITECTURE; DEMULTIPLEXING; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUITS; LAGRANGE MULTIPLIERS; MULTIPLEXING; ROUTING ALGORITHMS; THREE DIMENSIONAL;

NETWORK ARCHITECTURE;

EID: 77955691383     PISSN: 19430663     EISSN: None     Source Type: Journal    
DOI: 10.1109/LES.2009.2034710     Document Type: Article

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