-
1
-
-
0036149420
-
Networks on chips: A new SoC paradigm
-
L. Benini, and G.D. Micheli Networks on chips: a new SoC paradigm IEEE Computer 35 January 2002 70 78
-
(2002)
IEEE Computer
, vol.35
, Issue.JANUARY
, pp. 70-78
-
-
Benini, L.1
Micheli, G.D.2
-
2
-
-
0034848112
-
Route packets, not wires: On-chip interconnection networks
-
W.J. Dally, B. Towles, Route packets, not wires: on-chip interconnection networks, in: Proceedings of the Design Automation Conference, 2001, pp. 684-689.
-
(2001)
Proceedings of the Design Automation Conference
, pp. 684-689
-
-
Dally, W.J.1
Towles, B.2
-
3
-
-
36849066437
-
The distributed microarchitecture of the TRIPS prototype processor
-
K. Sankaralingam, R. Nagarajan, P. Gratz, R. Desikan, D. Gulati, H. Hanson, C. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P. Shivakumar, W. Yoder, R. McDonald, S. Keckler, D. Burger, The distributed microarchitecture of the TRIPS prototype processor, in: International Symposium on Microarchitectures, 2006, pp. 480-491.
-
(2006)
International Symposium on Microarchitectures
, pp. 480-491
-
-
Sankaralingam, K.1
Nagarajan, R.2
Gratz, P.3
Desikan, R.4
Gulati, D.5
Hanson, H.6
Kim, C.7
Liu, H.8
Ranganathan, N.9
Sethumadhavan, S.10
Sharif, S.11
Shivakumar, P.12
Yoder, W.13
McDonald, R.14
Keckler, S.15
Burger, D.16
-
4
-
-
34548858682
-
An 80-tile 1.28 TFLOPS network-on-chip in 65 nm CMOS
-
February
-
S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, P. Iyer, A. Singh, T. Jacob, S. Jain, S. Venkataraman, Y. Hoskote, N. Borkar, An 80-tile 1.28 TFLOPS network-on-chip in 65 nm CMOS, in: IEEE International Solid State Circuits Conference, February 2007, pp. 98-99.
-
(2007)
IEEE International Solid State Circuits Conference
, pp. 98-99
-
-
Vangal, S.1
Howard, J.2
Ruhl, G.3
Dighe, S.4
Wilson, H.5
Tschanz, J.6
Finan, D.7
Iyer, P.8
Singh, A.9
Jacob, T.10
Jain, S.11
Venkataraman, S.12
Hoskote, Y.13
Borkar, N.14
-
7
-
-
77955713435
-
Intel Corporation, A touchstone delta system description
-
Intel Corporation, A touchstone delta system description, in: Intel Advanced Information, 1991.
-
(1991)
Intel Advanced Information
-
-
-
8
-
-
0028513557
-
The turn model for adaptive routing
-
C.J. Glass, and L.M. Ni The turn model for adaptive routing Journal of the ACM 41 September 1994 874 902
-
(1994)
Journal of the ACM
, vol.41
, Issue.SEPTEMBER
, pp. 874-902
-
-
Glass, C.J.1
Ni, L.M.2
-
11
-
-
84893736605
-
Load distribution with the proximity congestion awareness in a network on chip
-
E. Nilsson, M. Millberg, J. Öberg, A. Jantsch, Load distribution with the proximity congestion awareness in a network on chip, in: Proceedings of the Design Automation and Test in Europe, 2003, p. 11126.
-
(2003)
Proceedings of the Design Automation and Test in Europe
, pp. 11126
-
-
E. Nilsson1
-
15
-
-
34547144376
-
DyXY-a proximity congestion-aware deadlock-free dynamic routing method for network on chip
-
M. Li, Q.-A. Zeng, W.-B. Jone, DyXY-a proximity congestion-aware deadlock-free dynamic routing method for network on chip, in: Proceedings of the Design Automation Conference, 2006, pp. 849-852.
-
(2006)
Proceedings of the Design Automation Conference
, pp. 849-852
-
-
Li, M.1
Zeng, Q.-A.2
Jone, W.-B.3
-
16
-
-
57749191721
-
Regional congestion awareness of load balance in network-on-chips
-
February
-
P. Gratz, B. Grot, S.W. Keckler, Regional congestion awareness of load balance in network-on-chips, in: International Symposium on High Performance Computer Architecture, February 2008, pp. 203-214.
-
(2008)
International Symposium on High Performance Computer Architecture
, pp. 203-214
-
-
Gratz, P.1
Grot, B.2
Keckler, S.W.3
-
17
-
-
77955711065
-
A low latency router supporting adaptivity for on-chip interconnects
-
J. Kim, D. Park, T. Theocharides, N. Vijaykkrishnan, C.R. Das, A low latency router supporting adaptivity for on-chip interconnects, in: International Symposium on Computer Architecture, 2005, pp. 150-161.
-
(2005)
International Symposium on Computer Architecture
, pp. 150-161
-
-
Kim, J.1
Park, D.2
Theocharides, T.3
Vijaykkrishnan, N.4
Das, C.R.5
-
18
-
-
84943681390
-
A survey of wormhole routing techniques in direct networks
-
L.M. Ni, P.K. McKinley, A survey of wormhole routing techniques in direct networks, IEEE Computer (1993) 62-76.
-
(1993)
IEEE Computer
, pp. 62-76
-
-
Ni, L.M.1
McKinley, P.K.2
-
22
-
-
33748595257
-
Improving routing efficiency for network-on-chip through contention-aware input selection
-
D. Wu, B.M. Al Hashimi, M.T. Schmitz, Improving routing efficiency for network-on-chip through contention-aware input selection, in: Proceedings of the 2006 Conference on Asia South Pacific Design Automation, 2006, pp. 36-41.
-
(2006)
Proceedings of the 2006 Conference on Asia South Pacific Design Automation
, pp. 36-41
-
-
Wu, D.1
Al Hashimi, B.M.2
Schmitz, M.T.3
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