BBVC-3D-NoC: An efficient 3D NoC architecture using bidirectional bisynchronous vertical channels

Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010

Volumn , Issue , 2010, Pages 452-453

  Ralimani, Amir Mohammad ^a,b   Liljeberg, Pasi ^b   Plosila, Juha ^b   Tenhunen, Hannu ^a,b  

^a TURKU CENTRE FOR COMPUTER SCIENCE   (Finland)

^b UNIVERSITY OF TURKU   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; 65NM TECHNOLOGY; BAND-WIDTH UTILIZATION; BI-DIRECTIONAL CHANNELS; HIGH-SPEED; INTER-LAYER COMMUNICATION; NOC ARCHITECTURES; PROPOSED ARCHITECTURES; ROUTABILITY; UNIDIRECTIONAL CHANNEL; VERTICAL CHANNELS;

ARCHITECTURE;

THREE DIMENSIONAL;

EID: 77957928299     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2010.21     Document Type: Conference Paper

References (7)

1. B. S. Feero and P. P. Pande, "Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation," IEEE Trans, on Computers, Vol. 58, No. 1, 2009, pp. 32-45.
2. J. Muttersbach et al., "Practical design of globally asynchronous locally synchronous systems," in Proc. of ASYNC 2000, pp. 52-59.
3. I. Loi et al., "Supporting vertical links for 3D networks-on-chip: Toward an automated design and analysis flow," in Proc. of Nano-Net 2007, pp. 1-5.
4. S. Pasricha, "Exploring serial vertical interconnects for 3D ICs," in Proc. of DAC2009, pp. 581-586.
5. T. Ono, and M. Greenstreet, "A Modular Synchronizing FIFO for NoCs," in Proc. of NoCS2009, pp. 224-233.
6. A. M. Rahmani et al, "Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips," in Proc. of VLSID 2009, pp. 157-162.
7. A. M. Rahmani et al., "NED: A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-chips Using Negative Exponential Distribution," Journal of Low Power Electronics, Vol. 5, No. 3, 2009, pp. 396-405.