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Volumn , Issue , 2008, Pages 134-141

Near-Optimal oblivious routing on Three-Dimensional mesh networks

Author keywords

[No Author keywords available]

Indexed keywords

3D MESHES; AVERAGE CASE; CHIP ARCHITECTURES; CHIP DESIGNS; CHIP MULTI PROCESSORS; DESIGN METRICS; DEVICE LAYERS; HIGHER DIMENSIONS; MESH NETWORKS; NEW OPPORTUNITIES; OBLIVIOUS ROUTING; OPTIMALITY; PENALTY FACTORS; SILICON INTEGRATIONS; THREE DIMENSIONS; THREE-DIMENSIONAL (3D); TRAFFIC PATTERNS; TWO-DIMENSIONAL; WORST-CASE THROUGHPUTS;

EID: 62349087103     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2008.4751852     Document Type: Conference Paper
Times cited : (26)

References (21)
  • 1
    • 0017441638 scopus 로고
    • A Large Scale, Homogeneous, Fully Distributed Parallel Machine
    • ACM Press
    • H. Sullivan, T. R. Bashkow, "A Large Scale, Homogeneous, Fully Distributed Parallel Machine", in Annual Symposium on Computer Architecture, ACM Press, 1977, pp. 105-117.
    • (1977) Annual Symposium on Computer Architecture , pp. 105-117
    • Sullivan, H.1    Bashkow, T.R.2
  • 11
    • 85008053864 scopus 로고    scopus 로고
    • An 80-Tile Sub-100-W TeraFLOPS Processsor in 65nm CMOS
    • Jan
    • S. Vangal et al, "An 80-Tile Sub-100-W TeraFLOPS Processsor in 65nm CMOS", in IEEE Journal of Solid State Circuits, Jan. 2008.
    • (2008) IEEE Journal of Solid State Circuits
    • Vangal, S.1
  • 12
    • 67649654659 scopus 로고    scopus 로고
    • Tile Processor: Embedded Multicore for Networking and Multimedia
    • Stanford, CA, Aug
    • A. Agarwal et al, "Tile Processor: Embedded Multicore for Networking and Multimedia", in Hot Chips 19, Stanford, CA, Aug. 2007.
    • (2007) Hot Chips 19
    • Agarwal, A.1
  • 13
    • 0034453365 scopus 로고    scopus 로고
    • Three-Dimensional Shared Memory Fabricated using Wafer Stacking Technology
    • Dec
    • K. Lee et al, "Three-Dimensional Shared Memory Fabricated using Wafer Stacking Technology", in IEDM Technical Digest, pages 165-168, Dec. 2000.
    • (2000) IEDM Technical Digest , pp. 165-168
    • Lee, K.1
  • 14
    • 0038236501 scopus 로고    scopus 로고
    • Three Dimensional Integration: Technology, Use, and Issues for Mixed-Signal Applications
    • May
    • L. Xue, C. C. Liu, H.-S. Kim, S. Kim, and S. Tiwari, "Three Dimensional Integration: Technology, Use, and Issues for Mixed-Signal Applications", IEEE Trans. on Electron Devices, 50:601-609, May 2003.
    • (2003) IEEE Trans. on Electron Devices , vol.50 , pp. 601-609
    • Xue, L.1    Liu, C.C.2    Kim, H.-S.3    Kim, S.4    Tiwari, S.5
  • 15
    • 28344452134 scopus 로고    scopus 로고
    • Demystifying 3D ICs: The Pros and Cons of Going Vertical
    • W. R. Davis et al, "Demystifying 3D ICs: The Pros and Cons of Going Vertical", In IEEE Design & Test of Computers, 22(6):498-510, 2005.
    • (2005) In IEEE Design & Test of Computers , vol.22 , Issue.6 , pp. 498-510
    • Davis, W.R.1
  • 16
    • 46049089466 scopus 로고    scopus 로고
    • A 3D Packaging Technology for 4Gbit Stacked DRAM with 3Gbps Data Transfer
    • M. Kawano et al, "A 3D Packaging Technology for 4Gbit Stacked DRAM with 3Gbps Data Transfer", in IEEE International Electron Devices, pp. 1-4, 2006.
    • (2006) IEEE International Electron Devices , pp. 1-4
    • Kawano, M.1
  • 20
    • 62349139008 scopus 로고    scopus 로고
    • Cisco taps processor array architecture for NPU
    • August 9
    • R. Wilson, "Cisco taps processor array architecture for NPU", EE Times, August 9, 2004
    • (2004) EE Times
    • Wilson, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.