-
1
-
-
0017441638
-
A Large Scale, Homogeneous, Fully Distributed Parallel Machine
-
ACM Press
-
H. Sullivan, T. R. Bashkow, "A Large Scale, Homogeneous, Fully Distributed Parallel Machine", in Annual Symposium on Computer Architecture, ACM Press, 1977, pp. 105-117.
-
(1977)
Annual Symposium on Computer Architecture
, pp. 105-117
-
-
Sullivan, H.1
Bashkow, T.R.2
-
2
-
-
85025263656
-
Universal Schemes for Parallel Communication
-
Milwaukee, MN
-
L. G. Valiant, G. J. Brebner, "Universal Schemes for Parallel Communication", in ACM Symposium on The Theory of Computing, pp. 263-277, Milwaukee, MN, 1981.
-
(1981)
ACM Symposium on The Theory of Computing
, pp. 263-277
-
-
Valiant, L.G.1
Brebner, G.J.2
-
3
-
-
0029194738
-
ROMM Routing on Mesh and Torus Networks
-
Santa Barbara, CA
-
T. Nesson, S. L. Johnsson, "ROMM Routing on Mesh and Torus Networks", in ACM Symposium on Parallel Algorithms and Architectures, Santa Barbara, CA, 1995, pp. 275-287.
-
(1995)
ACM Symposium on Parallel Algorithms and Architectures
, pp. 275-287
-
-
Nesson, T.1
Johnsson, S.L.2
-
4
-
-
27544463701
-
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks
-
D. Seo, A. Ali, W.-T. Lim, N. Rafique, M. Thottethodi, "Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks", in International Symposium on Computer Architecture, 2005, pp. 432-443.
-
(2005)
International Symposium on Computer Architecture
, pp. 432-443
-
-
Seo, D.1
Ali, A.2
Lim, W.-T.3
Rafique, N.4
Thottethodi, M.5
-
5
-
-
0036956932
-
Worst-Case Traffic for Oblivious Routing Functions
-
Winnipeg, Manitoba, Canada, August 10, 13
-
B. Towles, W. J. Dally, "Worst-Case Traffic for Oblivious Routing Functions", in ACM Symposium on Parallel Algorithms and Architectures, Winnipeg, Manitoba, Canada, August 10 - 13, 2002.
-
(2002)
ACM Symposium on Parallel Algorithms and Architectures
-
-
Towles, B.1
Dally, W.J.2
-
6
-
-
84955452760
-
Dynamic voltage scaling with links for power optimization of interconnection networks
-
Feb
-
L. Shang, L.S. Peh, N.K. Jha, "Dynamic voltage scaling with links for power optimization of interconnection networks", in Proceedings of the 9th IEEE International Symposium on High-Performance Computer Architecture (HPCA), pages 79-90, Feb 2003.
-
(2003)
Proceedings of the 9th IEEE International Symposium on High-Performance Computer Architecture (HPCA)
, pp. 79-90
-
-
Shang, L.1
Peh, L.S.2
Jha, N.K.3
-
8
-
-
84862144932
-
Power-driven design of router microarchitectures in on-chip networks
-
IEEE Computer Society
-
H. Wang, L.-S. Peh, and S. Malik, "Power-driven design of router microarchitectures in on-chip networks", in Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, page 105. IEEE Computer Society, 2003.
-
(2003)
Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture
, pp. 105
-
-
Wang, H.1
Peh, L.-S.2
Malik, S.3
-
9
-
-
84955456130
-
Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures
-
Anaheim, CA
-
M. B. Taylor, W. Lee, S. Amarasinghe, and A. Agarwal, "Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures", in International Symposium on High-Performance Computer Architecture (HPCA), pages 341-353, Anaheim, CA, 2003.
-
(2003)
International Symposium on High-Performance Computer Architecture (HPCA)
, pp. 341-353
-
-
Taylor, M.B.1
Lee, W.2
Amarasinghe, S.3
Agarwal, A.4
-
10
-
-
36348975404
-
Implementation and Evaluation of On-Chip Network Architectures
-
P. Gratz, C. Kim, R. McDonald, S. Keckler, and D. Burger, "Implementation and Evaluation of On-Chip Network Architectures", in International Conference on Computer Design (ICCD), 2006.
-
(2006)
International Conference on Computer Design (ICCD)
-
-
Gratz, P.1
Kim, C.2
McDonald, R.3
Keckler, S.4
Burger, D.5
-
11
-
-
85008053864
-
An 80-Tile Sub-100-W TeraFLOPS Processsor in 65nm CMOS
-
Jan
-
S. Vangal et al, "An 80-Tile Sub-100-W TeraFLOPS Processsor in 65nm CMOS", in IEEE Journal of Solid State Circuits, Jan. 2008.
-
(2008)
IEEE Journal of Solid State Circuits
-
-
Vangal, S.1
-
12
-
-
67649654659
-
Tile Processor: Embedded Multicore for Networking and Multimedia
-
Stanford, CA, Aug
-
A. Agarwal et al, "Tile Processor: Embedded Multicore for Networking and Multimedia", in Hot Chips 19, Stanford, CA, Aug. 2007.
-
(2007)
Hot Chips 19
-
-
Agarwal, A.1
-
13
-
-
0034453365
-
Three-Dimensional Shared Memory Fabricated using Wafer Stacking Technology
-
Dec
-
K. Lee et al, "Three-Dimensional Shared Memory Fabricated using Wafer Stacking Technology", in IEDM Technical Digest, pages 165-168, Dec. 2000.
-
(2000)
IEDM Technical Digest
, pp. 165-168
-
-
Lee, K.1
-
14
-
-
0038236501
-
Three Dimensional Integration: Technology, Use, and Issues for Mixed-Signal Applications
-
May
-
L. Xue, C. C. Liu, H.-S. Kim, S. Kim, and S. Tiwari, "Three Dimensional Integration: Technology, Use, and Issues for Mixed-Signal Applications", IEEE Trans. on Electron Devices, 50:601-609, May 2003.
-
(2003)
IEEE Trans. on Electron Devices
, vol.50
, pp. 601-609
-
-
Xue, L.1
Liu, C.C.2
Kim, H.-S.3
Kim, S.4
Tiwari, S.5
-
15
-
-
28344452134
-
Demystifying 3D ICs: The Pros and Cons of Going Vertical
-
W. R. Davis et al, "Demystifying 3D ICs: The Pros and Cons of Going Vertical", In IEEE Design & Test of Computers, 22(6):498-510, 2005.
-
(2005)
In IEEE Design & Test of Computers
, vol.22
, Issue.6
, pp. 498-510
-
-
Davis, W.R.1
-
16
-
-
46049089466
-
A 3D Packaging Technology for 4Gbit Stacked DRAM with 3Gbps Data Transfer
-
M. Kawano et al, "A 3D Packaging Technology for 4Gbit Stacked DRAM with 3Gbps Data Transfer", in IEEE International Electron Devices, pp. 1-4, 2006.
-
(2006)
IEEE International Electron Devices
, pp. 1-4
-
-
Kawano, M.1
-
17
-
-
17644378782
-
3D Processing Technology and Its Impact on IA32 Microprocessors
-
B. Black, D. Nelson, C.Webb, and N. Samra, "3D Processing Technology and Its Impact on IA32 Microprocessors", in Proc. International Conference on Computer Design, pages 316-318, 2004.
-
(2004)
Proc. International Conference on Computer Design
, pp. 316-318
-
-
Black, B.1
Nelson, D.2
Webb, C.3
Samra, N.4
-
19
-
-
33845914023
-
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
-
F. Li, C. Nicopoulos, T. Richardson, Y. Xie, V. Narayanan, and M. Kandemir, "Design and Management of 3D Chip Multiprocessors Using Network-in-Memory", in 33rd International Symposium on Computer Architecture (ISCA), pages 130-141, 2006.
-
(2006)
33rd International Symposium on Computer Architecture (ISCA)
, pp. 130-141
-
-
Li, F.1
Nicopoulos, C.2
Richardson, T.3
Xie, Y.4
Narayanan, V.5
Kandemir, M.6
-
20
-
-
62349139008
-
Cisco taps processor array architecture for NPU
-
August 9
-
R. Wilson, "Cisco taps processor array architecture for NPU", EE Times, August 9, 2004
-
(2004)
EE Times
-
-
Wilson, R.1
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