Plasma etch technologies for the development of ultra-small feature size transistor devices

Journal of Physics D: Applied Physics

Volumn 44, Issue 17, 2011, Pages

  Borah, D ^a,b   Shaw, M T ^a,b   Rasappa, S ^a,b   Farrell, R A ^a,b   O'Mahony, C ^a,b   Faulkner, C M ^a,b   Bosea, M ^a,b   Gleeson, P ^a,b   Holmes, J D ^a,b   Morris, M A ^a,b  

^a UNIVERSITY COLLEGE CORK   (Ireland)

^b TRINITY COLLEGE DUBLIN   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

CHAMBER DESIGN; CMOS DEVICES; COMPUTER PROCESSORS; CRYSTALLINE SILICONS; DIRECTED SELF-ASSEMBLY; ETCH PROCESS; ETCH PROFILE; ETCH SELECTIVITY; FEATURE SIZES; HIGH DEMAND; INFORMATION AND COMMUNICATION TECHNOLOGIES; NANO PATTERN; NANO SCALE; OPTIMIZATION TECHNIQUES; PATTERN TRANSFERS; PLANARIZATION; PLASMA ETCH; PLASMA TECHNOLOGY; POLYMER PATTERNS; RESIST PATTERN; RESIST THICKNESS; SECONDARY PROCESS; SECONDARY PROCESSING; SELECTIVE ETCH; TRANSISTOR DESIGNS; ULTRA-SMALL;

BLOCK COPOLYMERS; ELECTRON BEAM LITHOGRAPHY; INFORMATION TECHNOLOGY; NANOSTRUCTURED MATERIALS; NANOWIRES; PHASE SEPARATION; PHOTORESISTS; PLASMAS;

PLASMA DEPOSITION;

EID: 79954607730     PISSN: 00223727     EISSN: 13616463     Source Type: Journal    
DOI: 10.1088/0022-3727/44/17/174012     Document Type: Article

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