Tunable replica bits for dynamic variation tolerance in 8T SRAM arrays

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 4, 2011, Pages 797-805

  Raychowdhury, Arijit ^a   Geuskens, Bibiche M ^a   Bowman, Keith A ^a   Tschanz, James W ^a   Lu, Shih Lien L ^a   Karnik, Tanay ^a   Khellah, Muhammad M ^a   De, Vivek K ^a  

^a INTEL CORPORATION   (United States)

Author keywords

8T SRAM arrays; dynamic variations; error detection; resilient circuits; resilient design; resilient memory; resilient microprocessor; timing error; tunable replica bits

Indexed keywords

8T SRAM ARRAYS; DYNAMIC VARIATIONS; RESILIENT CIRCUITS; RESILIENT DESIGN; RESILIENT MEMORY; RESILIENT MICROPROCESSOR; TIMING ERROR; TUNABLE REPLICA BITS;

ERROR DETECTION; MICROPROCESSOR CHIPS; STATIC RANDOM ACCESS STORAGE; TIMING CIRCUITS;

VLSI CIRCUITS;

EID: 79953189649     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2108141     Document Type: Article

References (28)

1. R. Kumar and G. Hinton, "A family of 45 nm IA processors," in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 58-59.
2. L. Chang, D. M. Fried, J. Hergenrother, J. W. Sleight, R. H. Dennard, R. K. Montoye, L. Sekaric, S. J. McNab, A. W. Topol, C. D. Adams, K. W. Guarini, and W. Haensch, "Stable SRAM cell design for the 32 nm node and beyond," in Symp. VLSI Technology Dig. Tech. Papers, 2005, pp. 128-129. (Pubitemid 43897595)
3. Y. Morita, H. Fujiwara, H. Noguchi, Y. Iguchi, K. Nii, H. Kawaguchi, and M. Yoshimoto, "An area-conscious low-voltage-oriented 8T-SRAM design under DVS environment," in Symp. VLSI Circuits Dig. Tech. Papers, 2007, pp. 256-257. (Pubitemid 351306645)
4. L. Chang, Y. Nakamura, R. K. Montoye, J. Sawada, A. K. Martin, K. Kinoshita, F. H. Gebara, K. B. Agarwal, D. J. Acharyya, W. Haensch, K. Hosokawa, and D. Jamsek, "A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65 nm CMOS," in Symp. VLSI Circuits Dig. Tech. Papers, 2007, pp. 252-253. (Pubitemid 351306643)
5. K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y.Wang, B. Zheng, and M. Bohr, "A 3-GHz 70-Mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 146-151, Jan. 2006. (Pubitemid 43145972)
6. K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, H. Makino, Y. Yamagami, S. Ishikura, T. Terano, T. Oashi, K. Hashimoto, A. Sebe, G. Okazaki, K. Satomi, H. Akamatsu, and H. Shinohara, "A 45- nm bulk CMOS embedded SRAM with improved immunity against process and temperature variations," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 180-191, Jan. 2008.
7. S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, T.Yoshihara, M. Igarashi, M. Takeuchi, H. Kawashima, Y.Yamaguchi, K. Tsukamoto, M. Inuishi, H. Makino, K. Ishibashi, and H. Shinohara, "A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 820-829, Apr. 2007. (Pubitemid 46495399)
8. H. S. Yang, R. Wong, R. Hasumi, Y. Gao, N. S. Kim, D. H. Lee, S. Badrudduza, D. Nair, M. Ostermayr, H. Kang, H. Zhuang, J. Li, L. Kang, X. Chen, A. Thean, F. Arnaud, L. Zhuang, C. Schiller, D. P. Sun, Y. W. Teh, J. Wallner, Y. Takasu, K. Stein, S. Samavedam, D. Jaeger, C. V. Baiocco, M. Sherony, M. Khare, C. Lage, J. Pape, J. Sudijono, A. L. Steegen, and S. Stiffler, "Scaling of 32 nm low power SRAM with high-K metal gate," in Int. Electron Devices Meeting (IEDM) Tech. Dig., 2008, pp. 1-4.
9. A. Bhavnagarwala, S. Kosonocky, C. Radens, Y. Chan, K. Stawiasz, U. Srinivasan, S. P. Kowalczyk, and M. M. Ziegler, "A sub-600 mV, fluctuation tolerant 65- nm CMOS SRAM array with dynamic cell biasing," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 946-955, Apr. 2008.
10. T. Suzuki, H. Yamauchi, Y. Yamagami, and K. S. Akamatsu, "A stable 2-port SRAM cell design against simultaneously read/writedisturbed accesses," IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 2109-2119, Sep. 2008.
11. Y. Chung and S.-H. Song, "Implementation of low-voltage static RAM with enhance data stability and circuit speed," Microelectronics J., vol. 40, pp. 944-951, 2009.
12. Y. H. Chen, W. M. Chan, S. Y. Chou, H. J. Liao, H. Y. Pan, J. J. Wu, C. H. Lee, S. M. Yang, Y. C. Liu, and H. Yamauchi, "A 0.6 V 45 nm adaptive dual-rail SRAM compiler circuit design for lower VDD min VLSIs," in Symp. VLSI Circuits Dig. Tech. Papers, 2008, pp. 210-211.
13. B. Mohammad, M. Saint-Laurent, P. Bassett, and J. Abraham, "Cache design for low power and high yield," in Proc. 9th Int. Symp. Quality Electronic Design (ISQED), 2008, pp. 103-107.
14. K. Kushida, A. Suzuki, G. Fukano, A. Kawasumi, O. Hirabayashi, Y. Takeyama, T. Sasaki, A. Katayama, Y. Fujimura, and T. Yabe, "A 0.7 V single-supply SRAM with 0.495 μm P2P cell in 65 nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme," IEEE J.Solid-State Circuits, vol. 44, no. 4, pp. 1192-1198, Apr. 2009.
15. A. Raychowdhury, B. Geuskens, J. Kulkarni, J. Tschanz, K. Bowman, T. Karnik, S.-L. Lu, V. De, and M. M. Khellah, "PVT &aging adaptive word-line boosting for 8T SRAM power reduction," in IEEE ISSCC Dig. Tech. Papers, 2010, pp. 352-353.
16. N. Verma and A. P. Chandrakasan, "A 256 kb 65 nm 8T subthresold SRAM employing sense-amplifier redundancy," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 141-149, Jan. 2008.
17. I. J. Chang, J. J. Kim, S. P. Park, and K. Roy, "A 32 kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 388-622.
18. B. Zhai, D. Blaauw, D. Sylvester, and S. Hanson, "A sub-200 mV 6T SRAM in 0.13 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 332-606.
19. A. Muhtaroglu, G. Taylor, and T. R. Arabi, "On-die droop detector for analog sensing of power supply noise," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 651-660, Apr. 2004.
20. T. Fischer, J. Desai, B. Doyle, S. Naffziger, and B. Patella, "A 90-nm variable frequency clock system for a power-managed itanium architecture processor," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 218-228, Jan. 2006. (Pubitemid 43145979)
21. R. McGowen et al., "Power and temperature control on a 90-nm itanium family processor," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 229-237, Jan. 2006. (Pubitemid 43145980)
22. J. Tschanz et al., "Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 292-293.
23. Wang et al., "Techniques to extend canary-based standby VDD scaling for SRAMs to 45 nm and beyond," IEEE J. Solid-State Circuits, vol. 43, no. 11, p. 2514, Nov. 2008.
24. K. A. Bowman et al., "Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance," IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 49-63, Jan. 2009.
25. J. Tschanz et al., "Tunable replica circuits and adaptive voltage-frequency techniques for dynamic voltage, temperature, and aging variation tolerance," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, 2009, pp. 112-113.
26. J. Tschanz et al., "A 45 nm resilient and adaptive microprocessor core for dynamic variation tolerance," in IEEE ISSCC Dig. Tech. Papers, 2010, pp. 282-283.
27. K. Mistry et al., "A 45 nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging," in IEEE IEDM Tech. Dig., 2007, pp. 247-250.
28. ™ micro-architecture (nehalem) clocking," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1121-1129, Apr. 2009.