PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 352-353

  Raychowdhury, Arijit ^a   Geuskens, Bibiche ^a   Kulkarni, Jaydeep ^a   Tschanz, Jim ^a   Bowman, Keith ^a   Karnik, Tanay ^a   Lu, Shih Lien ^a   De, Vivek ^a   Khellah, Muhammad M ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

6T-CELL; 8T-CELL; BIT LINES; DUAL PORT; FAST READ; MICROPROCESSOR CORE; POWER REDUCTIONS; SINGLE-ENDED; SRAM CELL; WORDLINES;

ADAPTIVE BOOSTING; DYNAMIC RANDOM ACCESS STORAGE; MICROPROCESSOR CHIPS;

STATIC RANDOM ACCESS STORAGE;

EID: 77952207400     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433815     Document Type: Conference Paper

References (4)

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2. K. Mistry et al., "A 45 nm logic technology with high-k + metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging," in IEDM Tech. Dig., pp. 247-250, Dec. 2007.
3. Y. Morita et al., "An area-conscious low-voltage-oriented 8T-SRAM design under DVS environment," Symp. VLSI Circuits, pp. 256-257, Jun 2007.
4. Ming-Dou Ker et al., "Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes," IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1100-1107, May 2006.