Designing modular hardware accelerators in C with ROCCC 2.0

Proceedings - IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2010

Volumn , Issue , 2010, Pages 127-134

  Villarreal, Jason ^a   Park, Adrian ^a   Najjar, Walid ^b   Halstead, Robert ^b  

^a Jacquard Computing Inc   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

High level synthesis; C to VHDL; Compilers; FPGAs

Indexed keywords

APPLICATION CODES; APPLICATION DEVELOPERS; BOTTOM-UP DESIGN; C CODES; C PROGRAMS; CLOCK FREQUENCY; CODE GENERATION; COMMON SUBEXPRESSION ELIMINATION; CONFIGURABLE; ERROR PRONES; HARDWARE ACCELERATORS; HARDWARE DESCRIPTION LANGUAGES; HARDWARE OPTIMIZATION; HIGH LEVEL SYNTHESIS; LINES OF CODE; LOW LEVEL; MODULAR HARDWARE; OPTIMIZING COMPILERS; PROGRAMMABILITY; PROGRAMMING TIME; SOFTWARE SYSTEMS; SUPPORT FUNCTIONS; USER CONTROL;

COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SOFTWARE; COMPUTER SYSTEMS PROGRAMMING; COMPUTERS; HARDWARE; LINGUISTICS; PROGRAM COMPILERS; QUALITY CONTROL; QUERY LANGUAGES;

HIGH LEVEL LANGUAGES;

EID: 77954298772     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2010.28     Document Type: Conference Paper

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