Bit-level optimization for high-level synthesis and FPGA-based acceleration

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2010, Pages 59-68

  Zhang, Jiyu ^a,b,c   Zhang, Zhiru ^d   Zhou, Sheng ^d   Tan, Mingxing ^a   Liu, Xianhua ^a   Cheng, Xu ^a   Cong, Jason ^b,c  

^a PEKING UNIVERSITY   (China)

^b University of California   (United States)

^c PKU/UCLA Joint Research Institute in Science and Engineering   (China)

^d AutoESL Design Technologies   (United States)

Author keywords

Bit level optimization; FPGA; High level synthesis

Indexed keywords

CLOCK PERIOD; CONFIGURABLE COMPUTING; DATA-FLOW GRAPHS; FLOW GRAPH; HARDWARE DESCRIPTION LANGUAGES; HARDWARE DESIGN; HIGH LEVEL SYNTHESIS; HIGH-LEVEL PROGRAMMING LANGUAGE; LATENCY REDUCTION; LEVEL TRANSFORMATION; OPTIMIZATION APPROACH; SUBOPTIMAL IMPLEMENTATIONS;

ALGORITHMIC LANGUAGES; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DATA FLOW ANALYSIS; LINGUISTICS; LOGIC GATES; OPTIMIZATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 77951593778     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1723112.1723124     Document Type: Conference Paper

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