Pattern-based behavior synthesis for FPGA resource reduction

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2008, Pages 107-116

  Cong, Jason ^a   Jiang, Wei ^a  

^a University of California   (United States)

Author keywords

Behavior synthesis; FPGA; Pattern

Indexed keywords

BEHAVIOR SYNTHESIS; BIT-WIDTH; CHARACTERISTIC VECTORS; DATA PATHS; DESIGN OPTIMIZATION; EDIT DISTANCE; FPGA; GENERAL PATTERNS; GRAPH EDIT DISTANCE; LOCALITY SENSITIVE HASHING; PATTERN; PRUNING TECHNIQUES; RESOURCE BINDING; RESOURCE OPTIMIZATION; TWO-GRAPHS;

LOGIC GATES; MICROPROCESSOR CHIPS; PATTERN MATCHING; RESOURCE ALLOCATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 63349100795     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1344671.1344688     Document Type: Conference Paper

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