The new generation of soi mosfets

Romanian Journal of Information Science and Technology

Volumn 11, Issue 1, 2008, Pages 3-15

  Colinge, J P ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 79952673073     PISSN: 14538245     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (25)

1. Sekigawa T., Hayashi Y., Calculated Threshold-Voltage Characteristics Of An Xmos Transistor Having An Additional Bottom Gate, Solid-State Electronics, Vol. 27, P. 827, 198-4.
2. Balestra F., Cristoloveanu S., Benachir M., Brini J., Elewa T., Double-Gate Silicon-On-Insulator Transistor With Volume Inversion: A New Device With Greatly Enhanced Performance, Ieee Electron Device Letters, Vol. 8, No. 9, P. 410, 198-7.
3. Colinge J.P., Gao M.H., Romano A., Maes H., Claeys C., Silicon-On-Insulator ́Gate-All-Around' Mos Device, Technical Digest Of Iedm, P. 595, 199-0.
4. Hisamoto D., Kaga T., Kawamoto Y., Takeda E., A Fully Depleted Lean-Channel Transistor (Delta)-A Novel Vertical Ultra Thin Soi Mosfet, Technical Digest Of Iedm, P. 833, 198-9.
5. Hisamoto E., Lee W.C., Kedzierski J., Anderson E., Takeuchi H., Asano K., King T.J., Bokor J., Hu C., A Folded-Channel Mosfet For Deep-Sub-Tenth Micron Era, Technical Digest Of Iedm, P. 1032, 199-8.
6. Pretet J., Monfray S., Cristoloveanu S., Skotnicki T., Silicon-On-Nothing Mosfets: Performance, Short-Channel EEcts, And Backgate Coupling, Ieee Transactions On Electron Devices, Vol. 51, P. 240, 200-2.
7. Liu Y., Ishii K., Tsutsumi T., Masahara M., Suzuki E., Ideal Rectangu-Lar Cross-Section Si-Fin Channel Double-Gate Mosfets Fabricated Using Orientation-Dependent Wet Etching, Ieee Electron Device Letters, Vol. 24, No. 7, P. 484, 200-3..
8. Hiramoto T., Nano-Scale Silicon Mosfet: Towards Non-Traditional And Quantum Devices, Ieee International Soi Conference Proceedings, P. 8, 200-1.
9. Jiao Z., Salama A.T., A Fully Depleted Delta Channel Soi Nmosfet, Electrochem. Society Proceedings, Vol. 2001-3, P. 403, 200-1.
10. Skotnicki T., Heading For Decananometer Cmos -Is Navigation Among Icebergs Still A Viable Strategy?, Proceedings Of Essderc, P. 19, 200-0.
11. Yan R.H., Ourmazd A., Lee K.F., Scaling The Si Mosfet: From Bulk To Soi To Bulk, Ieee Trans. On Electron Devices, Vol. 39, No. 7, P. 1704, 199-2.
12. Lee C.-W., Yun S., Yu C.-G., Park J.-T., Colinge J.P., Device Design Guidelines For Nano-Scale Mugfets, Solid-State Electronics, Vol. 51, No. 3, P. 505, 200-7.
13. Lemme M.C., Mollenhauer T., Henschel W., Wahlbrink T., Baus M., Winkler O., Granzner R., Schwierz F., Spangenberg B., Kurz H., Subthreshold Behavior Of Triple-Gate Mosfets On Soi Material, Solid State Electronics, Vol. 48, P. 529, 200-4.
14. Colinge J.P., Baie X., Bayot V., Grivei E., A Silicon-On-Insulator Quantum Wire, Solid-State Electronics, Vol. 39, P. 49, 199-6.
15. Doyle B.S., Datta S., Doczy M., Jin B., Kavalieros J., Linton T., Murthy A., Rios R., Chau R., High Performance Fully-Depleted Tri-Gate Cmos Transistors, Ieee Edl, Vol. 24, No. 4, P. 263, 200-3..
16. Park J.T., Colinge J.P., Multiple-Gate Soi Mosfets: Device Design Guidelines, Ieee Trans. On Elect. Dev., Vol. 49, No. 12, P. 2222, 200-2.
17. Yang F.L., Chen H.Y., Cheng F.C., Huang C.C., Chang C.Y., Chiu H.K., Lee C.C., Chen C.C., Huang H.T., Chen C.J. Et Al., 25 Nm Cmos Omega Fets, Technical Digest Of Iedm, P. 255, 200-2.
18. Andrieu F., Dupre C., Rochette F., Faynot O., Tosti L., Buj C., Rou-Chouze E., Casse M., Ghyselen B., Cayrefourcq I. Et Al., 25 Nm Short And Narrow Strained Fdsoi With Tin/Hfo2 Gate Stack, Symposium On Vlsi Technology, Paper 16.4, 200-6.
19. Singh N., Agarwal A., Bera L.K., Liow T.Y., Yang R., Rustagi S.C., Tung C.H., Kumar R., Lo G.Q., Balasubramanian N., Kwong D.L., High-Performance Fully Depleted Silicon Nanowire (Diameter ≪ 5 Nm) Gate-All-Around Cmos Devices, Ieee Electron Device Letters Vol. 27, No. 5, P. 383, 200-6.
20. Omura Y., Horiguchi S., Tabe M., Kishi K., Quantum-Mechanical EEcts On The Threshold Voltage Of Ultrathin Soi Nmosfets, Ieee Electron Device Letters, Vol. 14, No. 12, P. 569, 199-3..
21. Poiroux T., Vinet M., Faynot O., Widiez J., Lolivier J., Ernst T., Pre-Vitali B., Deleonibus S., Multiple Gate Devices: Advantages And Challenges, Mi-Croelectronic Engineering, Vol. 80, P. 378, 200-5.
22. Colinge J.P., Alderman J.C., Xiong W., Cleavelin C.R., Quantum-Mechanical EEcts In Trigate Soi Mosfets, Ieee Ted, Vol. 53, No. 5, P. 1131, 200-6.
23. Colinge J.P., Quinn A.J., Floyd L., Redmond G., Alderman J.C., Xiong W., Cleavelin C.R., Schulz T., Schruefer K., Knoblinger G., Pa-Truno P., Low-Temperature Electron Mobility In Trigate Soi Mosfets, Ieee Edl, Vol. 27, No. 2, P. 120, 200-6.
24. Colinge J.P., Xiong W., Cleavelin C.R., Schulz T., Schräufer K., Matthews K., Patruno P., Room-Temperature Low-Dimensional EEcts In Pi-Gate Soi Mosfets, Ieee Edl, Vol. 27, No. 9, P. 775, 200-6.
25. Singh N., Lim F.Y., Fang W.W., Rustagi S.C., Bera L.K., Agarwal A., Tung C.H., Hoe K.M., Omampuliyur S.R., Tripathi D., Adeyeye A.O., Lo G.Q., Balasubramanian N., Kwong D.L., Ultra-Narrow Silicon Nanowire Gate-All-Around Cmos Device: Impact Of Diameter, Channel-Orientation And Low Temperature On Device Performance, Technical Digest Of Iedm, Paper 20.4, 200-6.