Room-temperature low-dimensional effects in Pi-Gate SOI MOSFETs

IEEE Electron Device Letters

Volumn 27, Issue 9, 2006, Pages 775-777

  Colinge, J P ^a   Xiong, Weize ^b   Cleavelin, C R ^b   Schulz, T ^c   Schrufer K ^c   Matthews, K ^d   Patruno, P ^e  

^a University of California   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c INFINEON TECHNOLOGIES AG   (Germany)

^d ATDF Inc   (United States)

^e PARC TECHNOLOGIQUE DES FONTAINES   (France)

Author keywords

MOSFETs; Quantum wires; Semiconductor device measurements; Silicon on insulator (SOI) technology

Indexed keywords

CIRCUIT OSCILLATIONS; GATES (TRANSISTOR); SEMICONDUCTOR QUANTUM WIRES; SILICON ON INSULATOR TECHNOLOGY; THERMAL EFFECTS;

LOW-DIMENSIONAL EFFECTS; SEMICONDUCTOR DEVICE MEASUREMENTS;

MOSFET DEVICES;

EID: 33748505443     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.881086     Document Type: Article

References (8)

1. J. P. Colinge, "Multiple-gate SOI MOSFETs," Solid State Electron., vol. 48, no. 6, pp. 897-905, Jun. 2004.
2. B. S. Doyle, S. Datta, M. Dockzy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau, "High performance fully-depleted tri-gate CMOS transistors," IEEE Electron Device Lett., vol. 24, no. 4, pp. 263-265, Apr. 2003.
3. M. Heuser, M. Baus, B. Hadam, O. Winkler, B. Spangenberg, R. Granzner, M. Lemme, and H. Kurz, "Fabrication of wire-MOSFETs on silicon-oninsulator substrate," Microelectron. Eng., vol. 61/62, pp. 613-618, 2002.
4. M. Lemme, T. Mollenhauer, W. Henschel, T. Wahlbrink, M. Heuser, M. Baus, O. Winkler, B. Spangenberg, R. Granzner, F. Schwierz, and H. Kurz, "Influence of channel width on n- and p-type nano-wire-MOSFETs on silicon on insulator substrate," Microelectron. Eng., vol. 67/68, pp. 810-817, 2003.
5. D. Lederer, V. Kilchytska, T. Rudenko, N. Collaert, D. Flandre, A. Dixit, K. De Meyer, and J.-P. Raskin, "FinFET analogue characterization from DC to 110 GHz," Solid State Electron., vol. 49, no. 9, pp. 1488-1496, Sep. 2005.
6. M. Prunnila, J. Ahopelto, and F. Gamiz, "Electron mobility and magneto transport study of ultra-thin channel double-gate Si MOSFETs," Solid State Electron., vol. 49, no. 9, pp. 1516-1521, Sep. 2005.
7. J. P. Colinge, J. C. Alderman, W. Xiong, and C. R. Cleavelin, "Quantum-mechanical effects in trigate SOI MOSFETs," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1131-1136, May 2006.
8. J. P. Colinge, A. J. Quinn, L. Floyd, G. Redmond, J. C. Alderman, W. Xiong, C. R. Cleavelin, T. Schulz, K. Schruefer, G. Knoblinger, and P. Patruno, "Low-temperature electron mobility in trigate SOI MOSFETs," IEEE Electron Device Lett., vol. 27, no. 2, pp. 120-122, Feb. 2006.