Aspect ratio trapping: A unique technology for integrating Ge and III-Vs with silicon CMOS

ECS Transactions

Volumn 33, Issue 6, 2010, Pages 963-976

  Fiorenza, J G ^a   Park, J S ^a   Hydrick, J M ^a   Li, J ^a   Li, J Z ^b   Curtin, M ^b   Carroll, M ^b   Lochtefeld, A ^b  

^a AmberWave Systems Corporation   (United States)

^b Amberwave Systetms Corporation   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GALLIUM ARSENIDE; GERMANIUM COMPOUNDS; III-V SEMICONDUCTORS; INDIUM PHOSPHIDE; MOSFET DEVICES; SEMICONDUCTING GALLIUM; SEMICONDUCTING INDIUM PHOSPHIDE; SI-GE ALLOYS; SILICON;

DISLOCATION DENSITIES; EPITAXIAL LATERAL OVERGROWTH; HIGH ASPECT RATIO; INFRARED IMAGERS; LATTICE-MISMATCHED; LOW-DISLOCATION DENSITY; MONOLITHICALLY INTEGRATED; THREADING DISLOCATION;

ASPECT RATIO;

EID: 79952641841     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.3487628     Document Type: Conference Paper

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