Measurement-to-modeling correlation of the power delivery network impedance of a microprocessor system

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 2004, Pages 221-224

  Aygün, Kemal ^a   Hill, Michael J ^a   Eilert, Kimberly D ^a   Radhakrishnan, Kaladhar ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATION; ELECTRIC IMPEDANCE; ELECTRIC POTENTIAL; ELECTRIC POWER DISTRIBUTION; FREQUENCIES; MATHEMATICAL MODELS; PHASE LOCKED LOOPS;

DOMAIN MEASUREMENTS; FUNCTIONAL SYSTEMS; POWER DELIVERY SYSTEMS; TRANSIENT DIE VOLTAGE;

MICROPROCESSOR CHIPS;

EID: 15944390249     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. "CPU Power Supply Impedance Profile Measurement Using FFT and Clock Gating," by A. Waizman, in the Proceedings of IEEE conference on EPEP, pp.29-32, 2003.
2. "Modeling and Analysis of Multichip Module Power Supply Planes" by K. Lee and A. Barber, IEEE Transactions on CPMT, part B, vol. 18, no. 4, pp 628-639, Nov. 1995.
3. "Resonant free power network design using extended adaptive voltage positioning (EAVP) methodology," by A. Waizman and C. Chung, in IEEE Transactions on Advanced Packaging, Volume: 24 Issue: 3, pp 236-244, Aug. 2001.