Design & validation of the Pentium® III and Pentium® 4 processors power delivery

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 220-223

  Rahal Arabi, Tawfik ^a   Taylor, Greg ^a   Ma, Matthew ^a   Webb, Clair ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC IMPEDANCE; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; SILICON WAFERS; SPURIOUS SIGNAL NOISE;

POWER SUPPLY IMPEDANCE MODEL; POWER SUPPLY NOISE; PROCESSORS POWER DELIVERY;

MICROPROCESSOR CHIPS;

EID: 0242611627     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. Jaya Bandyopadhyay, "Power Distribution and Decoupling Modeling of Multilayer Printed Circuit Board.", EPEP 1999 Proceedings
2. Teong-Guan Yew et al., "Design and Performance Evaluation of Chip Capacitors on Microprocessor Packaging" EPEP 1999 Proceedings