-
1
-
-
77952126213
-
A 3 bit/cell 32 Gb NAND flash memory at 34 nm with 6 MB/s program throughput and with dynamic 2 b/cell blocks configuration mode for a program throughput increase up to 13 MB/s
-
G. Marotta, A. Macerola, A. D'Alessandro, A. Torsi, C. Cerafogli, C. Lattaro, C. Musilli, D. Rivers, E. Sirizotti, F. Paolini, G. Imondi, G. Naso, G. Santin, L. Botticchio, L. De Santis, L. Pilolli, M. L. Gallese, M. Incarnati, M. Tiburzi, P. Conenna, S. Perugini, V. Moschiano, W. Di Francesco, M. Goldman, C. Haid, D. Di Cicco, D. Orlandi, F. Rori, M. Rossini, T. Vali, R. Ghodsi, and F. Roohparvar, "A 3 bit/cell 32 Gb NAND flash memory at 34 nm with 6 MB/s program throughput and with dynamic 2 b/cell blocks configuration mode for a program throughput increase up to 13 MB/s," in Proc. IEEE Int. Solid-State Circuits Conf., 2010, pp. 444-445.
-
(2010)
Proc. IEEE Int. Solid-State Circuits Conf.
, pp. 444-445
-
-
Marotta, G.1
MacErola, A.2
D'Alessandro, A.3
Torsi, A.4
Cerafogli, C.5
Lattaro, C.6
Musilli, C.7
Rivers, D.8
Sirizotti, E.9
Paolini, F.10
Imondi, G.11
Naso, G.12
Santin, G.13
Botticchio, L.14
De Santis, L.15
Pilolli, L.16
Gallese, M.L.17
Incarnati, M.18
Tiburzi, M.19
Conenna, P.20
Perugini, S.21
Moschiano, V.22
Di Francesco, W.23
Goldman, M.24
Haid, C.25
Di Cicco, D.26
Orlandi, D.27
Rori, F.28
Rossini, M.29
Vali, T.30
Ghodsi, R.31
Roohparvar, F.32
more..
-
2
-
-
70349291218
-
A 113 mm 32 Gb 3 b/cell NAND flash memory
-
Feb.
-
T. Futatsuyama, N. Fujita, N. Tokiwa, Y. Shindo, T. Edahiro, T. Kamei, H. Nasu, M. Iwai, K. Kato, Y. Fukuda, N. Kanagawa, N. Abiko, M. Matsumoto, T. Himeno, T. Hashimoto, Y.-C. Liu, H. Chibvongodze, T. Hori, M. Sakai, H. Ding, Y. Takeuchi, H. Shiga, N. Kajimura, Y. Kajitani, K. Sakurai, K. Yanagidaira, T. Suzuki, Y. Namiki, T. Fujimura, M. Mui, H. Nguyen, S. Lee, A. Mak, J. Lutze, T. Maruyama, T. Watanabe, T. Hara, and S. Ohshima, "A 113 mm 32 Gb 3 b/cell NAND flash memory," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2009, pp. 242-243.
-
(2009)
Proc. IEEE Int. Solid-State Circuits Conf.
, pp. 242-243
-
-
Futatsuyama, T.1
Fujita, N.2
Tokiwa, N.3
Shindo, Y.4
Edahiro, T.5
Kamei, T.6
Nasu, H.7
Iwai, M.8
Kato, K.9
Fukuda, Y.10
Kanagawa, N.11
Abiko, N.12
Matsumoto, M.13
Himeno, T.14
Hashimoto, T.15
Liu, Y.-C.16
Chibvongodze, H.17
Hori, T.18
Sakai, M.19
Ding, H.20
Takeuchi, Y.21
Shiga, H.22
Kajimura, N.23
Kajitani, Y.24
Sakurai, K.25
Yanagidaira, K.26
Suzuki, T.27
Namiki, Y.28
Fujimura, T.29
Mui, M.30
Nguyen, H.31
Lee, S.32
Mak, A.33
Lutze, J.34
Maruyama, T.35
Watanabe, T.36
Hara, T.37
Ohshima, S.38
more..
-
3
-
-
58149250393
-
A 16 Gb 3-bit per cell (X3) NAND flash memory on 56 nm technology with 8 MB/s write rate
-
Jan.
-
S. Lee, Y. Fong, F. Pan, T.-C. Kuo, J. Park, T. Samaddar,H. T. Nguyen, L. Mui, K. Htoo, T. Kamei, M. Higashitani, E.Yero, G.Kwon, P. Kliza, J. Wan, T. Kaneko, H. Maejima, H. Shiga, M. Hamada, N. Fujita, K. Kanebako, E. Tam, A. Koh, I. Lu, C.-H. Kuo, T. Pham, J. Huynh, Q. Nguyen, H. Chibvongodze, M. Watanabe, K. Oowada, G. Shah, B. Woo, R. Gao, J. Chan, J. Lan, P. Hong, L. Peng, D. Das, D. Ghosh, V. Kalluru, S. Kulkarni, R.-A. Cernea, S. Huynh, D. Pantelakis, C.-M. Wang, and K. Quader, "A 16 Gb 3-bit per cell (X3) NAND flash memory on 56 nm technology with 8 MB/s write rate," IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 195-207, Jan. 2009.
-
(2009)
IEEE J. Solid-State Circuits
, vol.44
, Issue.1
, pp. 195-207
-
-
Lee, S.1
Fong, Y.2
Pan, F.3
Kuo, T.-C.4
Park, J.5
Samaddar, T.6
Nguyen, H.T.7
Mui, L.8
Htoo, K.9
Kamei, T.10
Higashitani, M.11
Yero, E.12
Kwon, G.13
Kliza, P.14
Wan, J.15
Kaneko, T.16
Maejima, H.17
Shiga, H.18
Hamada, M.19
Fujita, N.20
Kanebako, K.21
Tam, E.22
Koh, A.23
Lu, I.24
Kuo, C.-H.25
Pham, T.26
Huynh, J.27
Nguyen, Q.28
Chibvongodze, H.29
Watanabe, M.30
Oowada, K.31
Shah, G.32
Woo, B.33
Gao, R.34
Chan, J.35
Lan, J.36
Hong, P.37
Peng, L.38
Das, D.39
Ghosh, D.40
Kalluru, V.41
Kulkarni, S.42
Cernea, R.-A.43
Huynh, S.44
Pantelakis, D.45
Wang, C.-M.46
Quader, K.47
more..
-
4
-
-
41549092721
-
A 70 nm 16 Gb 16-Level-Cell NAND flash memory
-
Apr.
-
H. Maejima, K. Isobe, K. Iwasa, M. Nakagawa, M. Fujiu, T. Shimizu, M. Honma, S. Hoshi, T. Kawaai, K. Kanebako, S. Yoshikawa, H. Tabata, A. Inoue, T. Takahashi, T. Shano, Y. Komatsu, K. Nagaba, M. Kosakai, N. Motohashi, K. Kanazawa, K. Imamiya, H. Nakai, M. Lasser, M. Murin, A. Meir, A. Eyal, and M. Shlick, "A 70 nm 16 Gb 16-Level-Cell NAND flash memory," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 929-937, Apr. 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.4
, pp. 929-937
-
-
Maejima, H.1
Isobe, K.2
Iwasa, K.3
Nakagawa, M.4
Fujiu, M.5
Shimizu, T.6
Honma, M.7
Hoshi, S.8
Kawaai, T.9
Kanebako, K.10
Yoshikawa, S.11
Tabata, H.12
Inoue, A.13
Takahashi, T.14
Shano, T.15
Komatsu, Y.16
Nagaba, K.17
Kosakai, M.18
Motohashi, N.19
Kanazawa, K.20
Imamiya, K.21
Nakai, H.22
Lasser, M.23
Murin, M.24
Meir, A.25
Eyal, A.26
Shlick, M.27
more..
-
5
-
-
70349271258
-
A 5.6 MB/s 64 Gb 4 b/Cell NAND flash memory in 43 nm CMOS
-
Feb.
-
N. Shibata, T. Nakano, M. Ogawa, J. Sato, Y. Takeyama, K. Isobe, B. Le, F. Mooga, N. Mokhlesi, K. Kozakai, P. Hong, T. Kamei, K. Iwasa, J. Nakai, T. Shimizu, M. Honma, S. Sakai, T. Kawaai, S. Hoshi, J. Yuh, C. Hsu, T. Tseng, J. Li, J. Hu, M. Liu, S. Khalid, J. Chen, M. Watanabe, H. Lin, J. Yang, K. McKay, K. Nguyen, T. Pham, Y. Matsuda, K. Nakamura, K. Kanebako, S.Yoshikawa,W. Igarashi, A. Inoue, T. Takahashi, Y. Komatsu, C. Suzuki, K. Kanazawa, M. Higashitani, S. Lee, T. Murai, K. Nguyen, J. Lan, S. Huynh, M. Murin, M. Shlick, M. Lasser, R. Cernea, M. Mofidi, K. Schuegraf, and K. Quader, "A 5.6 MB/s 64 Gb 4 b/Cell NAND flash memory in 43 nm CMOS," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2009, pp. 246-247.
-
(2009)
Proc. IEEE Int. Solid-State Circuits Conf.
, pp. 246-247
-
-
Shibata, N.1
Nakano, T.2
Ogawa, M.3
Sato, J.4
Takeyama, Y.5
Isobe, K.6
Le, B.7
Mooga, F.8
Mokhlesi, N.9
Kozakai, K.10
Hong, P.11
Kamei, T.12
Iwasa, K.13
Nakai, J.14
Shimizu, T.15
Honma, M.16
Sakai, S.17
Kawaai, T.18
Hoshi, S.19
Yuh, J.20
Hsu, C.21
Tseng, T.22
Li, J.23
Hu, J.24
Liu, M.25
Khalid, S.26
Chen, J.27
Watanabe, M.28
Lin, H.29
Yang, J.30
McKay, K.31
Nguyen, K.32
Pham, T.33
Matsuda, Y.34
Nakamura, K.35
Kanebako, K.36
Igarashi, S.37
Yoshikawa, W.38
Inoue, A.39
Takahashi, T.40
Komatsu, Y.41
Suzuki, C.42
Kanazawa, K.43
Higashitani, M.44
Lee, S.45
Murai, T.46
Nguyen, K.47
Lan, J.48
Huynh, S.49
Murin, M.50
Shlick, M.51
Lasser, M.52
Cernea, R.53
Mofidi, M.54
Schuegraf, K.55
Quader, K.56
more..
-
7
-
-
77957556492
-
Improving multi-level NAND flash memory storage reliability using concatenated BCH-TCM coding
-
Oct.
-
S. Li and T. Zhang, "Improving multi-level NAND flash memory storage reliability using concatenated BCH-TCM coding," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 10, pp. 1412-1420, Oct. 2010.
-
(2010)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
, vol.18
, Issue.10
, pp. 1412-1420
-
-
Li, S.1
Zhang, T.2
-
8
-
-
84925405668
-
Low-density parity-check codes
-
Jan.
-
R. G. Gallager, "Low-density parity-check codes," IRE Trans. Inf. Theory, vol. IT-8, no. 1, pp. 21-28, Jan. 1962.
-
(1962)
IRE Trans. Inf. Theory
, vol.IT-8
, Issue.1
, pp. 21-28
-
-
Gallager, R.G.1
-
9
-
-
0033099611
-
Good error-correcting codes based on very sparse matrices
-
Mar.
-
D. J. C. MacKay, "Good error-correcting codes based on very sparse matrices," IEEE Trans. Inf. Theory, vol. 45, no. 2, pp. 399-431, Mar. 1999.
-
(1999)
IEEE Trans. Inf. Theory
, vol.45
, Issue.2
, pp. 399-431
-
-
MacKay, D.J.C.1
-
10
-
-
0033183669
-
Improved decoding of Reed-Solomon and algebraic-geometry codes
-
Sep.
-
V. Guruswami and M. Sudan, "Improved decoding of Reed-Solomon and algebraic-geometry codes," IEEE Trans. Inf. Theory, vol. 45, no. 6, pp. 1757-1767, Sep. 1999.
-
(1999)
IEEE Trans. Inf. Theory
, vol.45
, Issue.6
, pp. 1757-1767
-
-
Guruswami, V.1
Sudan, M.2
-
11
-
-
0345306775
-
Algebraic soft-decision decoding of Reed-Solomon codes
-
Nov.
-
R. Koetter and A. Vardy, "Algebraic soft-decision decoding of Reed-Solomon codes," IEEE Trans. Inf. Theory, vol. 49, no. 11, pp. 2809-2825, Nov. 2003.
-
(2003)
IEEE Trans. Inf. Theory
, vol.49
, Issue.11
, pp. 2809-2825
-
-
Koetter, R.1
Vardy, A.2
-
12
-
-
0027297425
-
Near Shannon limit error-correcting coding and decoding: Turbo-codes
-
Geneve, Switzerland, May
-
C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon limit error-correcting coding and decoding: Turbo-codes," in Proc. ICC, Geneve, Switzerland, May 1993, pp. 1064-1070.
-
(1993)
Proc. ICC
, pp. 1064-1070
-
-
Berrou, C.1
Glavieux, A.2
Thitimajshima, P.3
-
14
-
-
49049108116
-
Future memory technology: Challenges and opportunities
-
Apr.
-
K. Kim, "Future memory technology: Challenges and opportunities," in Proc. Int. Symp. VLSI Technol., Syst., Appl., Apr. 2008, pp. 5-9.
-
(2008)
Proc. Int. Symp. VLSI Technol., Syst., Appl.
, pp. 5-9
-
-
Kim, K.1
-
16
-
-
67650098640
-
3D simulation study of cell-cell interference in advanced NAND flash memory
-
Apr.
-
H. Liu, S. Groothuis, C. Mouli, J. Li, K. Parat, and T. Krishnamohan, "3D simulation study of cell-cell interference in advanced NAND flash memory," in Proc. IEEE Workshop Microelectron. Electron Devices, Apr. 2009, pp. 1-3.
-
(2009)
Proc. IEEE Workshop Microelectron. Electron Devices
, pp. 1-3
-
-
Liu, H.1
Groothuis, S.2
Mouli, C.3
Li, J.4
Parat, K.5
Krishnamohan, T.6
-
17
-
-
41549125910
-
A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories
-
Apr.
-
K.-T. Park, M. Kang, D. Kim, S.-W. Hwang, B. Y. Choi, Y.-T. Lee, C. Kim, and K. Kim, "A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 919-928, Apr. 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.4
, pp. 919-928
-
-
Park, K.-T.1
Kang, M.2
Kim, D.3
Hwang, S.-W.4
Choi, B.Y.5
Lee, Y.-T.6
Kim, C.7
Kim, K.8
-
18
-
-
0030123707
-
th select gate array architecture for multilevel NAND flash memories
-
Apr.
-
th select gate array architecture for multilevel NAND flash memories," IEEE J. Solid-State Circuits, vol. 31, no. 4, pp. 602-609, Apr. 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, Issue.4
, pp. 602-609
-
-
Takeuchi, K.1
Tanaka, T.2
Nakamura, H.3
-
19
-
-
0029404872
-
A 3.3 v 32 Mb NAND flash memory with incremental step pulse programming scheme
-
Nov.
-
K.-D. Suh, B.-H. Suh, Y.-H. Lim, J.-K. Kim, Y.-J. Choi, Y.-N. Koh, S.-S. Lee, S.-C. Kwon, B.-S. Choi, J.-S. Yum, J.-H. Choi, J.-R. Kim, and H.-K. Lim, "A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme," IEEE J. Solid-State Circuits, vol. 30, no. 11, pp. 1149-1156, Nov. 1995.
-
(1995)
IEEE J. Solid-State Circuits
, vol.30
, Issue.11
, pp. 1149-1156
-
-
Suh, K.-D.1
Suh, B.-H.2
Lim, Y.-H.3
Kim, J.-K.4
Choi, Y.-J.5
Koh, Y.-N.6
Lee, S.-S.7
Kwon, S.-C.8
Choi, B.-S.9
Yum, J.-S.10
Choi, J.-H.11
Kim, J.-R.12
Lim, H.-K.13
-
20
-
-
3142773890
-
Introduction to flash memory
-
Apr.
-
R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, "Introduction to flash memory," Proc. IEEE, vol. 91, no. 4, pp. 489-502, Apr. 2003.
-
(2003)
Proc. IEEE
, vol.91
, Issue.4
, pp. 489-502
-
-
Bez, R.1
Camerlenghi, E.2
Modelli, A.3
Visconti, A.4
-
21
-
-
69949152635
-
Random telegraph noise effect on the programmed threshold-voltage distribution of flash memories
-
Sep.
-
C. M. Compagnoni, M. Ghidotti, A. L. Lacaita, A. S. Spinelli, and A. Visconti, "Random telegraph noise effect on the programmed threshold-voltage distribution of flash memories," IEEE Electron Device Lett., vol. 30, no. 9, pp. 984-986, Sep. 2009.
-
(2009)
IEEE Electron Device Lett.
, vol.30
, Issue.9
, pp. 984-986
-
-
Compagnoni, C.M.1
Ghidotti, M.2
Lacaita, A.L.3
Spinelli, A.S.4
Visconti, A.5
-
22
-
-
64549097141
-
Scaling trends for random telegraph noise in deca-nanometer flash memories
-
A. Ghetti, C. M. Compagnoni, F. Biancardi, A. L. Lacaita, S. Beltrami, L. Chiavarone, A. S. Spinelli, and A. Visconti, "Scaling trends for random telegraph noise in deca-nanometer flash memories," in IEDM Tech. Dig., 2008, pp. 1-4.
-
(2008)
IEDM Tech. Dig.
, pp. 1-4
-
-
Ghetti, A.1
Compagnoni, C.M.2
Biancardi, F.3
Lacaita, A.L.4
Beltrami, S.5
Chiavarone, L.6
Spinelli, A.S.7
Visconti, A.8
-
23
-
-
0036575326
-
Effects of floating-gate interference on NAND flash memory cell operation
-
May
-
J.-D. Lee, S.-H. Hur, and J.-D. Choi, "Effects of floating-gate interference on NAND flash memory cell operation," IEEE Electron Device Lett., vol. 23, no. 5, pp. 264-266, May 2002.
-
(2002)
IEEE Electron Device Lett.
, vol.23
, Issue.5
, pp. 264-266
-
-
Lee, J.-D.1
Hur, S.-H.2
Choi, J.-D.3
-
24
-
-
33846216331
-
2 8-Gb multi-level NAND flash memory with 10-MB/s program throughput
-
Jan.
-
2 8-Gb multi-level NAND flash memory with 10-MB/s program throughput," IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 219-232, Jan. 2007.
-
(2007)
IEEE J. Solid-State Circuits
, vol.42
, Issue.1
, pp. 219-232
-
-
Kameda, Y.1
Fujimura, S.2
Otake, H.3
Hosono, K.4
Shiga, H.5
Watanabe, Y.6
Futatsuyama, T.7
Shindo, Y.8
Kojima, M.9
Iwai, M.10
Shirakawa, M.11
Ichige, M.12
Hatakeyama, K.13
Tanaka, S.14
Kamei, T.15
Fu, J.-Y.16
Cernea, A.17
Li, Y.18
Higashitani, M.19
Hemink, G.20
Sato, S.21
Oowada, K.22
Lee, S.-C.23
Hayashida, N.24
Wan, J.25
Lutze, J.26
Tsao, S.27
Mofidi, M.28
Sakurai, K.29
Tokiwa, N.30
Waki, H.31
Nozawa, Y.32
Kanazawa, K.33
Ohshima, S.34
more..
-
25
-
-
49549098189
-
A 16 Gb 3 b/cell NAND flash memory in 56 nm with 8 MB/s write rate
-
Feb.
-
S. Lee, Y. Fong, F. Pan, T.-C. Kuo, J. Park, T. Samaddar, H. Nguyen, M. Mui, K. Htoo, T. Kamei, M. Higashitani, E. Yero, G. Kwon, P. Kliza, J.Wan, T. Kaneko, H. Maejima, H. Shiga, M. Hamada, N. Fujita, K. Kanebako, A. Koh, I. Lu, C. Kuo, T. Pham, J. Huynh, Q. Nguyen, H. Chibvongodze, M. Watanabe, K. Oowada, G. Shah, B. Woo, R. Gao, J. Chan, J. Lan, P. Hong, L. Peng, D. Das, D. Ghosh, V. Kalluru, S. Kulkarni, R. Cernea, S. Huynh, D. Pantelakis, C.-M. Wang, and K. Quader, "A 16 Gb 3 b/cell NAND flash memory in 56 nm with 8 MB/s write rate," in Proc. IEEE ISSCC, Feb. 2008, pp. 506-632.
-
(2008)
Proc. IEEE ISSCC
, pp. 506-632
-
-
Lee, S.1
Fong, Y.2
Pan, F.3
Kuo, T.-C.4
Park, J.5
Samaddar, T.6
Nguyen, H.7
Mui, M.8
Htoo, K.9
Kamei, T.10
Higashitani, M.11
Yero, E.12
Kwon, G.13
Kliza, P.14
Wan, J.15
Kaneko, T.16
Maejima, H.17
Shiga, H.18
Hamada, M.19
Fujita, N.20
Kanebako, K.21
Koh, A.22
Lu, I.23
Kuo, C.24
Pham, T.25
Huynh, J.26
Nguyen, Q.27
Chibvongodze, H.28
Watanabe, M.29
Oowada, K.30
Shah, G.31
Woo, B.32
Gao, R.33
Chan, J.34
Lan, J.35
Hong, P.36
Peng, L.37
Das, D.38
Ghosh, D.39
Kalluru, V.40
Kulkarni, S.41
Cernea, R.42
Huynh, S.43
Pantelakis, D.44
Wang, C.-M.45
Quader, K.46
more..
-
26
-
-
58149267843
-
A 34 MB/s MLC write throughput 16 Gb NAND with all bit line architecture on 56 nm technology
-
Jan.
-
L. Pham, F. Moogat, S. Chan, B. Le, Y. Li, S. Tsao, T.-Y. Tseng, K. Nguyen, J. Li, J. Hu, J.H. Yuh, C. Hsu, F. Zhang, T. Kamei, H. Nasu, P. Kliza, K. Htoo, J. Lutze, Y. Dong, M. Higashitani, J. Yang, H.-S. Lin, V. Sakhamuri, A. Li, F. Pan, S. Yadala, S. Taigor, K. Pradhan, J. Lan, J. Chan, T. Abe, Y. Fukuda, H. Mukai, K. Kawakami, C. Liang, T. Ip, S.-F. Chang, J. Lakshmipathi, S. Huynh, D. Pantelakis, M. Mofidi, and K. Quader, "A 34 MB/s MLC write throughput 16 Gb NAND with all bit line architecture on 56 nm technology," IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 186-194, Jan. 2009.
-
(2009)
IEEE J. Solid-State Circuits
, vol.44
, Issue.1
, pp. 186-194
-
-
Pham, L.1
Moogat, F.2
Chan, S.3
Le, B.4
Li, Y.5
Tsao, S.6
Tseng, T.-Y.7
Nguyen, K.8
Li, J.9
Hu, J.10
Yuh, J.H.11
Hsu, C.12
Zhang, F.13
Kamei, T.14
Nasu, H.15
Kliza, P.16
Htoo, K.17
Lutze, J.18
Dong, Y.19
Higashitani, M.20
Yang, J.21
Lin, H.-S.22
Sakhamuri, V.23
Li, A.24
Pan, F.25
Yadala, S.26
Taigor, S.27
Pradhan, K.28
Lan, J.29
Chan, J.30
Abe, T.31
Fukuda, Y.32
Mukai, H.33
Kawakami, K.34
Liang, C.35
Ip, T.36
Chang, S.-F.37
Lakshmipathi, J.38
Huynh, S.39
Pantelakis, D.40
Mofidi, M.41
Quader, K.42
more..
-
27
-
-
77957898678
-
Using data postcompensation and predistortion to tolerate cell-to-cell interference in MLC NAND flash memory
-
Oct.
-
G. Dong, S. Li, and T. Zhang, "Using data postcompensation and predistortion to tolerate cell-to-cell interference in MLC NAND flash memory," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 10, pp. 2718-2728, Oct. 2010.
-
(2010)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.57
, Issue.10
, pp. 2718-2728
-
-
Dong, G.1
Li, S.2
Zhang, T.3
-
28
-
-
59049087539
-
On the distribution of the sum of independent uniform random variables
-
Jan.
-
S. M. Sadooghi-Alvandi, A. R. Nematollahi, and R. Habibi, "On the distribution of the sum of independent uniform random variables," Stat. Papers, vol. 50, no. 1, pp. 171-174, Jan. 2009.
-
(2009)
Stat. Papers
, vol.50
, Issue.1
, pp. 171-174
-
-
Sadooghi-Alvandi, S.M.1
Nematollahi, A.R.2
Habibi, R.3
-
29
-
-
18144396564
-
Block-LDPC: A practical LDPC coding system design approach
-
Apr.
-
H. Zhong and T. Zhang, "Block-LDPC: A practical LDPC coding system design approach," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 4, pp. 766-775, Apr. 2005.
-
(2005)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.52
, Issue.4
, pp. 766-775
-
-
Zhong, H.1
Zhang, T.2
-
30
-
-
79551512177
-
Fast, low-power reading of data in a flash memory
-
Dec. 24
-
I. Alrod and M. Lasser, "Fast, low-power reading of data in a flash memory," U.S. Patent 2 009 031 987 2A1, Dec. 24, 2009.
-
(2009)
U.S. Patent 2009 031 987 2A1
-
-
Alrod, I.1
Lasser, M.2
-
32
-
-
67650413689
-
Novel FEXT cancellation and equalization for high speed ethernet transmission
-
Jun.
-
J. Chen, Y. Gu, and K. K. Parhi, "Novel FEXT cancellation and equalization for high speed ethernet transmission," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 6, pp. 906-912, Jun. 2009.
-
(2009)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.56
, Issue.6
, pp. 906-912
-
-
Chen, J.1
Gu, Y.2
Parhi, K.K.3
|