Improving multi-level NAND flash memory storage reliability using concatenated BCH-TCM coding

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 10, 2010, Pages 1412-1420

  Li, Shu ^a   Zhang, Tong ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

Error rate; fault tolerance; hardware cost; throughput; trellis coded modulation (TCM)

Indexed keywords

65-NM NODE; BASIC IDEA; BCH CODE; CODING SYSTEM; CORRECTION PERFORMANCE; DESIGN PRACTICE; ERROR RATE; HARDWARE COST; MEMORY CELL; MEMORY FAULT TOLERANCE; MULTI-LEVEL; NAND FLASH MEMORY; PRACTICAL IMPLEMENTATION; SILICON IMPLEMENTATION; STATIC MEMORY; STORAGE CHARACTERISTIC; STORAGE DENSITIES; STORAGE RELIABILITY; TECHNOLOGY SCALING; TRELLIS CODED MODULATION;

BIT ERROR RATE; COMPUTER HARDWARE; COMPUTER SIMULATION; DESIGN; FAULT TOLERANCE; FITS AND TOLERANCES; MODULATION; NAND CIRCUITS; QUALITY ASSURANCE; SEMICONDUCTOR STORAGE;

FLASH MEMORY;

EID: 77957556492     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2024154     Document Type: Article

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