A 5GHz floating point multiply-accumulator in 90nm dual VT CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 333-335+497

  Vangal, Sriram ^a   Hoskote, Yatin ^a   Somasekhar, Dinesh ^a   Erraguntla, Vasantha ^a   Howard, Jason ^a   Ruhl, Gregory ^a   Veeramachaneni, Venkat ^a   Finan, David ^a   Mathew, Sanu ^a   Borkar, Nitin ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; BUFFER CIRCUITS; COMPUTER SIMULATION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; MICROPROCESSOR CHIPS;

ACCUMULATOR MANTISSA LOOP; FLOATING POINT MULTIPLY ACCUMULATOR; LEADING ZERO ANTICIPATOR; OVERFLOW DETECTION; TOGGLE DETECTION CIRCUIT;

CMOS INTEGRATED CIRCUITS;

EID: 0038645279     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. IEEE Standards Board, "IEEE Standard for Binary Floating-Point Arithmetic," Technical Report ANSI/IEEE Std. 754-1985, IEEE, New York, 1985.
2. Z. Luo, et al., "Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques," IEEE Trans. on Computers, Mar. 2000 pp 208-218.
3. H. Suzuki et al., "Leading-Zero Anticipatory Logic for High-speed Floating Point Addition," IEEE J. Solid State Circuits, Aug. 1996, pp. 1157-1164.
4. S. Mathew, et al., "A 4GHz 130nm Address Generation Unit with a 32-bit Sparse-tree Adder Core," VLSI Circuits Symp. 2002, pp. 126-127.
5. F. Klass, "Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic," VLSI Circuits Symp. 1998, Digest of Technical Papers, pp 108-109.