-
1
-
-
0031247861
-
Tunneling devices and applications in high functionality/speed digital circuits
-
G.I. Haddad, and P. Mazumder Tunneling devices and applications in high functionality/speed digital circuits Solid State Electron 41 10 1997 1515 1524
-
(1997)
Solid State Electron
, vol.41
, Issue.10
, pp. 1515-1524
-
-
Haddad, G.I.1
Mazumder, P.2
-
2
-
-
0000900676
-
Digital circuit applications of resonant tunneling devices
-
P. Mazumder, S. Kulkarni, M. Bhattacharya, P.S. Jian, and G.I. Haddad Digital circuit applications of resonant tunneling devices Proc IEEE 86 1998 664 686
-
(1998)
Proc IEEE
, vol.86
, pp. 664-686
-
-
Mazumder, P.1
Kulkarni, S.2
Bhattacharya, M.3
Jian, P.S.4
Haddad, G.I.5
-
3
-
-
31344434389
-
Resonant tunnelling delta sigma modulator suitable for high-speed operation
-
K. Maezawa, M. Sakou, W. Matsubara, and T. Mizutani Resonant tunnelling delta sigma modulator suitable for high-speed operation Electron Lett 42 2 2006 77 78
-
(2006)
Electron Lett
, vol.42
, Issue.2
, pp. 77-78
-
-
Maezawa, K.1
Sakou, M.2
Matsubara, W.3
Mizutani, T.4
-
4
-
-
0014707790
-
Superlattice and negative differential conductivity in semiconductors
-
L. Esaki, and R. Tsu Superlattice and negative differential conductivity in semiconductors IBM J Res Develop 14 1 1970 61 65
-
(1970)
IBM J Res Develop
, vol.14
, Issue.1
, pp. 61-65
-
-
Esaki, L.1
Tsu, R.2
-
8
-
-
0037321217
-
Logic synthesis and circuit modeling of a programmable logic gate based on controlled quenching of series-connected negative differential devices
-
K.J. Chen, and G. Niu Logic synthesis and circuit modeling of a programmable logic gate based on controlled quenching of series-connected negative differential devices IEEE J Solid-State Circuits 38 2003 312 318
-
(2003)
IEEE J Solid-State Circuits
, vol.38
, pp. 312-318
-
-
Chen, K.J.1
Niu, G.2
-
10
-
-
0026903981
-
A new resonant-tunnel diode-based multivalued memory circuit using a MESFET depletion load
-
Z.X. Yan, and M.J. Deen A new resonant-tunnel diode-based multivalued memory circuit using a MESFET depletion load IEEE J Solid-St Circuits 27 1992 1198 1202
-
(1992)
IEEE J Solid-St Circuits
, Issue.27
, pp. 1198-1202
-
-
Yan, Z.X.1
Deen, M.J.2
-
12
-
-
4444341306
-
Tri-state logic using vertically integrated Si resonant interband tunneling diodes with double NDR
-
N. Jin, S.Y. Chung, R.M. Heyns, P.R. Berger, R. Yu, and P.E. Thompson Tri-state logic using vertically integrated Si resonant interband tunneling diodes with double NDR IEEE Electron Dev Lett 25 2004 646 648
-
(2004)
IEEE Electron Dev Lett
, vol.25
, pp. 646-648
-
-
Jin, N.1
Chung, S.Y.2
Heyns, R.M.3
Berger, P.R.4
Yu, R.5
Thompson, P.E.6
-
13
-
-
0041409587
-
Diffusion barrier cladding in Si/SiGe RITDs and their patterned growth on PMOS source/drain regions
-
N. Jin, S.Y. Chung, A.T. Rice, P.R. Berger, P.E. Thompson, and C. Rivas Diffusion barrier cladding in Si/SiGe RITDs and their patterned growth on PMOS source/drain regions IEEE Trans Electron Dev 50 2003 1876 1884 [Special issue "Nanoelectronics"]
-
(2003)
IEEE Trans Electron Dev
, vol.50
, pp. 1876-1884
-
-
Jin, N.1
Chung, S.Y.2
Rice, A.T.3
Berger, P.R.4
Thompson, P.E.5
Rivas, C.6
-
14
-
-
0000323725
-
Si/SiGe electron resonant tunneling diodes
-
D.J. Paul, P. See, I.V. Zozoulenko, K.F. Berggren, B. Kabius, and B. Hollander Si/SiGe electron resonant tunneling diodes Appl Phys Lett 77 2000 1653 1655
-
(2000)
Appl Phys Lett
, vol.77
, pp. 1653-1655
-
-
Paul, D.J.1
See, P.2
Zozoulenko, I.V.3
Berggren, K.F.4
Kabius, B.5
Hollander, B.6
-
15
-
-
3142765641
-
Monolithically integrated Si/SiGe resonant interband tunnel diode/CMOS demonstrating low voltage MOBILE operation
-
S. Sudirgo, R.P. Nandgaonkar, B. Curanovic, J.L. Hebding, R.L. Saxer, and S.S. Islam Monolithically integrated Si/SiGe resonant interband tunnel diode/CMOS demonstrating low voltage MOBILE operation Solid State Electron 48 2004 1907 1910
-
(2004)
Solid State Electron
, vol.48
, pp. 1907-1910
-
-
Sudirgo, S.1
Nandgaonkar, R.P.2
Curanovic, B.3
Hebding, J.L.4
Saxer, R.L.5
Islam, S.S.6
-
16
-
-
2342620672
-
Three-terminal Si-based negative differential resistance circuit element with adjustable peak-to-valley current ratios using a monolithic vertical integration
-
S.Y. Chung, N. Jin, P.R. Berger, R. Yu, P.E. Thompson, and R. Lake Three-terminal Si-based negative differential resistance circuit element with adjustable peak-to-valley current ratios using a monolithic vertical integration Appl Phys Lett 84 2004 2688 2690
-
(2004)
Appl Phys Lett
, vol.84
, pp. 2688-2690
-
-
Chung, S.Y.1
Jin, N.2
Berger, P.R.3
Yu, R.4
Thompson, P.E.5
Lake, R.6
-
17
-
-
34247575233
-
Fabrication and application of MOS-HBT-NDR circuit using standard SiGe process
-
K.J. Gan, C.S. Tsai, and W.L. Sun Fabrication and application of MOS-HBT-NDR circuit using standard SiGe process Electron Lett 43 9 2007 516 517
-
(2007)
Electron Lett
, vol.43
, Issue.9
, pp. 516-517
-
-
Gan, K.J.1
Tsai, C.S.2
Sun, W.L.3
-
18
-
-
0018678815
-
Integrated Λ-type differential negative resistance MOSFET device
-
C.Y. Wu, and K.N. Lai Integrated Λ-type differential negative resistance MOSFET device IEEE J Solid-State Circuits 14 1979 1094 1101
-
(1979)
IEEE J Solid-State Circuits
, vol.14
, pp. 1094-1101
-
-
Wu, C.Y.1
Lai, K.N.2
-
19
-
-
33646398921
-
Four-valued memory circuit using three-peak MOS-NDR devices and circuits
-
K.J. Gan, Y.H. Chen, C.S. Tsai, and L.X. Su Four-valued memory circuit using three-peak MOS-NDR devices and circuits Electron Lett 42 9 2006 21 22
-
(2006)
Electron Lett
, vol.42
, Issue.9
, pp. 21-22
-
-
Gan, K.J.1
Chen, Y.H.2
Tsai, C.S.3
Su, L.X.4
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